BT261 datasheet(14/56 Pages) ETC

14 / 56 page

Bt261

30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller

Brooktree®

CIRCUIT DESCRIPTION

CLAMP and ZERO Outputs

L261_H

CLAMP and ZERO Outputs

The CLAMP and ZERO outputs are provided to control the clamping and zero tim-

ing of the A/D converter or Image Digitizer. The start and stop timing is program-

mable by the MPU (in pixel clock cycles). ZERO is used to autocalibrate the

comparators of the A/D converter or Image Digitizer. CLAMP is used to DC-re-

store the video signal. Both CLAMP and ZERO may be programmed to be either

active high or active low.

Capture Output

The Bt261 outputs a CAPTURE signal, which is a command register bit (CR05)

synchronized to the vertical sync or FIELD signals.

To capture a single frame of video in an interlaced system, the MPU resets the

capture bit (CR5) low, then sets it high before the next rising edge of ﬁeld. At the

rising edge of FIELD, the CAPTURE output will be set to a logical zero until the

next rising edge of FIELD (one frame time), when the CAPTURE output is set

high.

In a non-interlaced system, the MPU resets the capture bit (CR5) low, then sets

it high before the falling edge of VSYNC*. When the falling edge of VSYNC* oc-

curs, the capture output will be set high until the next falling edge of VSYNC*.

BT261 Datasheet(PDF) 14 Page - List of Unclassifed Manufacturers