BT261 datasheet(24/56 Pages) ETC

24 / 56 page

Bt261

30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller

Brooktree®

CIRCUIT DESCRIPTION

Pin Descriptions

L261_H

Table 2. Pin Descriptions Grouped By Pin Function

Pin Name

Description

HSYNC

Horizontal sync input/output (TTL compatible). As an output, HSYNC is programmed to be

either a logical zero or logical one during the desired horizontal sync interval. It is output fol-

lowing the rising edge of CLOCK. As an input, it is input into the phase comparator asyn-

chronously to the clocks with no pipeline delays.

VSYNC*

Vertical sync output (TTL compatible) with a negative composite sync output. VSYNC* is a

logical zero for scan lines during detected vertical sync intervals on the VIDEO input. It is

output following the rising edge of CLOCK.

CSYNC*

Composite sync output (TTL compatible). CSYNC* is a logical zero during negative com-

posite sync intervals detected on the VIDEO input. It is output asynchronous to the clocks

with no pipeline delays.

ZERO

Zero output (TTL compatible). This output is used to control the ZERO input of the image

digitizer or A/D converter. It may be programmed to be either active high or active low and is

output following the rising edge of CLOCK.

CLAMP

Clamp output (TTL compatible). This output is used to control the CLAMP input of the

image digitizer or A/D converter. It may be programmed to be either active high or active low

and is output following the rising edge of CLOCK.

FIELD

Even/odd ﬁeld output (TTL compatible). For interlaced operation, this output (with transi-

tions coincident with the VSYNC* output) indicates whether the current ﬁeld is even or odd;

the polarity is programmable. For noninterlaced operation, this output is always either a log-

ical one or a logical zero, depending on whether it is programmed to be active high or low. It

is output on the falling edge of VSYNC*.

PCOUT

Phase comparator output (TTL compatible). This three-state output indicates the phase dif-

ference in time between the generated horizontal sync signal (either the internally generated

HSYNC or the HSYNC pin) and the recovered horizontal sync signal. High = lags, Low =

leads.

VIDEO

Video and composite sync input. Either a DC-coupled TTL composite sync information or

an AC-coupled analog video signal (less than 2 V peak-to-peak) may be input via this pin for

detection of sync information. Sync information must be of negative polarity.

CLOCK

Pixel clock input/output (TTL compatible). The device may either drive this pin with a gener-

ated clock or an external pixel clock may drive this pin. When the CLOCK pin is externally

driven, the selected OSC pin must also be driven.

OSC1, OSC1*,

OSC2, OSC2*

External clock inputs (TTL or ECL compatible). These inputs are programmed to be either

TTL or ECL compatible (10KH differential ECL driven by a single +5 V supply).

CAPTURE

Active video output (TTL compatible). This output is active high for a frame duration and is

synchronized to the vertical sync interval and FIELD signal. It is output following the rising

edge of FIELD for interlaced, or the falling edge of VSYNC* if non-interlaced.

RD*

Read control input (TTL compatible). If RD* is a logical zero, data is output onto D0–D7.

RD* and WR* should not be asserted simultaneously.

Pin Descriptions

BT261 Datasheet(PDF) 24 Page - List of Unclassifed Manufacturers

BT261 Datasheet(HTML) 24 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL