BT261 datasheet(22/56 Pages) ETC

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Bt261

30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller

Brooktree®

CIRCUIT DESCRIPTION

Asynchronous (Unlocked) Pixel Clock Generation

L261_H

Asynchronous (Unlocked) Pixel Clock Generation

Four oscillator clock inputs are provided (OSC), selectable by the MPU, conﬁg-

urable as either TTL or differential ECL inputs (designed to be driven by 10KH

ECL using a single +5 V supply).

The selected OSC input is divided down to the desired pixel clock rate and duty

cycle. The pixel clock low and high times are programmable by the MPU (as a

function of OSC clock cycles) via the OSC count low and high registers. Note that

both the rising and falling edge of the OSC inputs are used when specifying the

OSC count (for example, values of 2 for the OSC count low and high registers will

divide the OSC clock symmetrically by two).

The generated pixel clock is synchronized to the falling edge of the noise-gated

CSYNC* each scan line. Each time a horizontal sync is detected on the VIDEO in-

put, the CLOCK output is resynchronized by the OSC clock so that the beginning

of a pixel clock cycle and the falling edge of the noise-gated CSYNC* are coinci-

dent (see Figure 7) within one half the period of the OSC input. While there is

some sampling jitter on CLOCK associated with the falling edge of CSYNC*, the

residual jitter in the remaining line interval is strictly a function of the OSC clock

source jitter, symmetry, and amplitude/slew rate jitter, at the OSC input. Differen-

tial OSC signals of fast edges will minimize the latter contribution.

There are three ways of controlling the horizontal counter, as determined by

command bit CR07 and CR06.

CR07 and CR06 are (0,1): if a falling edge of the noise-gated CSYNC* does

not occur before the number of pixel clock cycles speciﬁed by HCOUNT, the hor-

izontal counter stops at the HCOUNT value and is held there until the next falling

edge of the noise-gated CSYNC*, at which time it is reset to zero. CLOCK stops

in the high state at the HCOUNT value, until the next falling edge of the noise-gat-

ed CSYNC*.

Figure 6. PLL Performance Can Be Monitored Using SR05

BT261 Datasheet(PDF) 22 Page - List of Unclassifed Manufacturers