AT91 datasheet(123/153 Pages) ATMEL

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AT91X40 Series

1354D–ATARM–08/02

Signal Name Description

Note:

After a hardware reset, the Timer Counter block pins are controlled by the PIO Controller. They must be configured to be con-

trolled by the peripheral before being used.

Timer Counter

Description

The three Timer Counter channels are independent and identical in operation. The reg-

isters for channel programming are listed in Table 17.

Counter

Each Timer Counter channel is organized around a 16-bit counter. The value of the

counter is incremented at each positive edge of the selected clock. When the counter

has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the bit

COVFS in TC_SR (Status Register) is set.

The current value of the counter is accessible in real-time by reading TC_CV. The

counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on

the next valid edge of the selected clock.

Clock Selection

At block level, input clock signals of each channel can either be connected to the exter-

nal inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals

TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode).

Each channel can independently select an internal or external clock source for its

counter:

•

Internal clock signals: MCK/2, MCK/8, MCK/32,

MCK/128, MCK/1024

•

External clock signals: XC0, XC1 or XC2

Channel Signal

Description

XC0, XC1, XC2

External Clock Inputs

TIOA

Capture Mode: General Purpose Input

Waveform Mode: General Purpose Output

TIOB

Capture Mode: General Purpose Input

Waveform Mode: General Purpose Input/Output

INT

Interrupt Signal Output

SYNC

Synchronization Input Signal

Block Signals

Description

TCLK0, TCLK1, TCLK2

External Clock Inputs

TIOA0

TIOA Signal for Channel 0

TIOB0

TIOB Signal for Channel 0

TIOA1

TIOA Signal for Channel 1

TIOB1

TIOB Signal for Channel 1

TIOA2

TIOA Signal for Channel 2

TIOB2

TIOB Signal for Channel 2

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