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AT91 Datasheet(PDF) 131 Page - ATMEL Corporation |
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AT91 Datasheet(HTML) 131 Page - ATMEL Corporation |
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131 / 153 page ![]() 131 AT91X40 Series 1354D–ATARM–08/02 TC User Interface TC Base Address: 0xFFFE0000 (Code Label TC_BASE) TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the TC block. TC Channels are controlled by the registers listed in Table 17. The offset of each of the Channel registers in Table 17 is in relation to the offset of the corresponding channel as mentioned in Table 16. Note: Read Only if WAVE = 0 Table 16. TC Global Memory Map Offset Channel/Register Name Access Reset State 0x00 TC Channel 0 See Table 17 0x40 TC Channel 1 See Table 17 0x80 TC Channel 2 See Table 17 0xC0 TC Block Control Register TC_BCR Write Only – 0xC4 TC Block Mode Register TC_BMR Read/Write 0 Table 17. TC Channel Memory Map Offset Register Name Access Reset State 0x00 Channel Control Register TC_CCR Write Only – 0x04 Channel Mode Register TC_CMR Read/Write 0 0x08 Reserved – 0x0C Reserved – 0x10 Counter Value TC_CV Read/Write 0 0x14 Register A TC_RA Read/Write(1) 0 0x18 Register B TC_RB Read/Write(1) 0 0x1C Register C TC_RC Read/Write 0 0x20 Status Register TC_SR Read Only 0 0x24 Interrupt Enable Register TC_IER Write Only – 0x28 Interrupt Disable Register TC_IDR Write Only – 0x2C Interrupt Mask Register TC_IMR Read Only 0 |
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