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CLRC663 Datasheet(PDF) 111 Page - NXP Semiconductors

Part # CLRC663
Description  High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
PDF  177 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

CLRC663 Datasheet(HTML) 111 Page - NXP Semiconductors

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NXP Semiconductors
CLRC663
High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
9.17.3 RxSyncValH
Bit
7
6
5
4
3
2
1
0
Symbol
RxSyncValH
Access
rights
r/w
Table 235. RxSyncValH register (address5Ah)
Bit
Symbol
Description
7 to 0
RxSyncValH
Defines the high byte of the Start Of Frame (SOF) pattern, which must be in front of the
receiving data.
Table 236. RxSyncValH bits
9.17.4 RxSyncValL
Bit
7
6
5
4
3
2
1
0
Symbol
RxSyncValL
Access
rights
r/w
Table 237. RxSyncValL register (address 5Bh)
Bit
Symbol
Description
7 to 0
RxSyncValL
Defines the low byte of the Start Of Frame (SOF) Pattern, which must be in front of the
receiving data.
Table 238. RxSyncValL bits
9.17.5 RxSyncMod
Bit
7
6
5
4
3
2
1
0
Symbol
SyncLen
SyncNegEdge
LastSyncHalf
SyncType
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rights
r/w
r/w
r/w
r/w
Table 239. RxSyncMode register (address 5Ch)
Bit
Symbol
Description
7 to 4
SyncLen
Defines how many Bits of registers RxSyncValH and RxSyncValL are valid. For ISO/IEC
14443B set to 0.
3
SyncNegEdge
Is used for SOF with no correlation peak. The first negative edge of the correlation is
used for defining the bit grid.
2
LastSyncHalf
The last Bit of the Sync mode has only half of the length compared to all other bits.
(ISO/IEC 18000-3 mode 3/ EPC Class-1HF).
1 to 0
SyncType
0: all 16 bits of SyncVal are interpreted as burst.
Table 240. RxSyncMod bits
CLRC663
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 5.3 — 3 January 2024
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