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ADPL76030 Datasheet(PDF) 28 Page - Analog Devices |
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ADPL76030 Datasheet(HTML) 28 Page - Analog Devices |
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28 / 40 page ![]() Data Sheet ADPL76030 analog.com Rev.0 28 of 40 RSENSE(BOOST) = 2 × 50 mV × VIN(MAX) 2 × IOUT(MAX) × VOUT + ∆IL(BOOST) × VIN(MIN) The maximum current sense RSENSE in the buck region is: RSENSE(BUCK) = 2 × 50 mV 2 × IOUT(MAX) + ∆IL(BUCK) The final RSENSE value should be lower than the calculated RSENSE in both the buck and boost regions. A 20% to 30% margin is usually recommended. Always choose a low ESL current-sense resistor. Power MOSFET Selection The ADPL76030 requires four external N-channel power MOSFETs, two for the top switches (switches A and D in Figure 35) and two for the bottom switches (switches B and C in Figure 35). Important parameters for the power MOSFETs are the breakdown voltage VBR(DSS), threshold voltage VGS(TH), on-resistance RDS(ON), reverse transfer capacitance CRSS, and maximum current IDS(MAX). To achieve 1.4 MHz operation, the power MOSFET selection is critical. With typical 25 ns shoot-through protection deadtime, high performance power MOSFETs with low Qg and low RDS(ON) must be used. Since the gate drive voltage is set by the 5 V INTVCC supply, logic-level threshold MOSFETs must be used in ADPL76030 applications. Switching four MOSFETs at higher frequency like 1.4 MHz, the substantial gate charge current from INTVCC can be estimated as: IINTVCC = f × (QgA + QgB + QgC + QgD) where: f is the switching frequency. QgA, QgB, QgC, QgD are the total gate charges of MOSFETs A, B, C, D. Make sure the total required INTVCC current does not exceed the INTVCC current limit in the data sheet. Typically, MOSFETs with less than 10 nC Qg are recommended. The ADPL76030 uses the VIN/VOUT ratio to transition between modes and regions. Bigger IR drop in the power path caused by improper MOSFET and inductor selection may prevent the ADPL76030 from smooth transition. To ensure smooth transitions between buck, buck-boost, and boost modes of operation, choose low RDS(ON)MOSFETs and low DCR inductor to satisfy: IOUT(MAX) ≤ 0.025 × VOUT RA,B + RC,D + RSENSE + RL where: RA,B is the maximum RDS(ON) of MOSFETs A or B at 25°C. RC,D is the maximum RDS(ON) of MOSFETs C or D at 25°C. RLis the maximum DCR resistor of inductor at 25°C. The RDS(ON) and DCR increase at higher junction temperatures and the process variations are included in the calculation above. |
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