Data Sheet

ADPL76030

analog.com

Rev.0

26 of 40

Figure 43. Average Conducted EM

Figure 44. Peak Conducted EMI

Frequency Synchronization

The ADPL76030 switching frequency can be synchronized to an external clock using the SYNC/SPRD pin. Driving the

SYNC/SPRD with a 50% duty cycle waveform is always a good choice. Otherwise, maintain the duty cycle between

10% and 90%. Due to the use of a phase-locked loop (PLL) inside, there is no restriction between the synchronization

frequency and internal oscillator frequency. The rising edge of the synchronization clock represents the beginning

of a switching cycle, turning on switches A and C, or switches A and D.

Inductor Selection

The switching frequency and inductor selection are interrelated in that higher switching frequencies allow the use of

smaller inductor and capacitor values. The inductor value has a direct effect on ripple current. The highest current

ripple ∆IL% happens in the buck region at VIN(MAX), and the lowest current ripple ∆IL% happens in the boost region at

VIN(MIN). For any given ripple allowance set by customers, the minimum inductance can be calculated as:

LBUCK >

VOUT × (VIN(MAX) − VOUT)

f × IOUT(MAX) × ∆IL% × VIN(MAX)

LBOOST >

VIN(MIN)

2 × (V

OUT − VIN(MIN))

f × IOUT(MAX) × ∆IL% × VOUT

2

FREQUENCY (MHz)

0.1

1

10

SSFM ON WITH EMI FILTER

NOISE FLOOR

CISPER 25 CLASS 5 PEAK LIMITS

LW

MW

SW

CB

80

90

70

60

50

40

30

20

10

0

–10

FREQUENCY (MHz)

80

90

70

60

50

40

30

20

10

0

–10

0.1

1

10

SSFM ON WITH EMI FILTER

NOISE FLOOR

CISPER 25 CLASS 5 PEAK LIMITS

LW

MW

SW

CB