Data Sheet

ADPL76030

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Rev.0

23 of 40

Shutdown and Power-On-Reset

The ADPL76030 enters shutdown mode and drains less than 2 µA quiescent current when the EN/UVLO pin is below

its shutdown threshold (0.3 V minimum). Once the EN/UVLO pin is above its shutdown threshold (1 V maximum), the

ADPL76030 wakes up start-up circuitry, generates bandgap reference, and powers up the internal INTVCC LDO. The

INTVCC LDO supplies the internal control circuitry and gate drivers. Now the ADPL76030 enters undervoltage lockout

(UVLO) mode with a hysteresis current (2.5 µA typical) pulled into the EN/UVLO pin. When the INTVCC pin is charged

above its rising UVLO threshold (3.78 V typical), the EN/UVLO pin passes its rising enable threshold (1.233 V typical),

and the junction temperature is less than its thermal shutdown (165°C typical), the ADPL76030 enters enable mode,

in which the EN/UVLO hysteresis current is turned off and the voltage reference VREF is charged up from ground. From

the time of entering enable mode to the time of VREF passing its rising UVLO threshold (1.89 V typical), the ADPL76030

is going through a power-on-reset (POR), waking up the entire internal control circuitry and settling to the right initial

conditions.

Start-Up and Fault Protection

Figure 42 shows the start-up and fault sequence for the ADPL76030. During the POR state, the SS pin is hard pulled

down with a 100 Ω to ground. In a pre-biased condition, the SS pin must be pulled below 0.2 V to enter the INIT state,

where the ADPL76030 waits 10 µs so that the SS pin can be fully discharged to ground. After the 10 µs, the ADPL76030

enters the UP/PRE state. The LOADON high signal happens when the CTRL pin is above its rising latch-off thresholds

(0.325 V typical).

Figure 42. Start-Up and Fault Sequence

During the UP/PRE state, the SS pin is charged up by a 12.5 µA pull-up current while the switching is disabled. Once

the SS pin is charged above 0.25 V, the ADPL76030 enters the UP/TRY state, while the switching is still disabled. If an

excessive current flowing through the current-sense resistor triggers the ISP/ISN over current (ISOC) signal, it resets

the ADPL76030 back into the POR state. After 10 µs in the UP/TRY state without triggering the ISOC signal, the

ADPL76030 enters the UP/RUN state.

POR

• SS HARD PULL DOWN

• SWITCHING DISABLED

• NO SHORT DETECTION

INIT

• SS HARD PULL DOWN

• SWITCHING DISABLED

• NO SHORT DETECTION

POR = HI OR

ISOC = HI

SS < 0.2V

UP/TRY

• SS 12.5µA PULL UP

• SWITCHING DISABLED

• NO SHORT DETECTION

UP/PRE

• SS 12.5µA PULL UP

• SWITCHING DISABLED

• NO SHORT DETECTION

WAIT 10µs AND

LOADON = HI

SS > 0.25V

UP/RUN

• SS 12.5µA PULL UP

• SWITCHING ENABLED

• NO SHORT DETECTION

OK/RUN

• SS 12.5µA PULL UP

• SWITCHING ENABLED

• SHORT DETECTION

WAIT 10µs

SS > 1.75V

DOWN/STOP

• SS 1.25µA PULL DOWN

• SWITCHING DISABLED

• NO SHORT DETECTION

FAULT/RUN

• SS 1.25µA PULL DOWN

• SWITCHING ENABLED

• SHORT DETECTION

SS < 0.2V AND

LOADON = HI

SHORT

SS < 1.7V