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ADPL76030 Datasheet(PDF) 11 Page - Analog Devices |
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ADPL76030 Datasheet(HTML) 11 Page - Analog Devices |
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11 / 40 page ![]() Data Sheet ADPL76030 analog.com Rev.0 11 of 40 9 VREF Voltage Reference Output. The VREF pin provides an accurate 2 V reference capable of supplying 1 mA current. Locally bypass this pin to ground with a 0.47 µF ceramic capacitor 10 CTRL Control Input for ISP/ISN Current-Sense Threshold. The CTRL pin is used to program the ISP/ISN current limit: ������������������(������������������) = ������������������(������������������������������ − 0.25 ������, 1 ������) 10 × ������������������ The VCTRL can be set by an external voltage reference or a resistor divider from VREF to ground. For 0.3 V ≤ VCTRL ≤ 1.15 V, the current-sense threshold linearly goes up from 5 mV to 90 mV. For VCTRL ≥ 1.35 V, the current-sense threshold is constant at 100 mV full scale value. For 1.15 V ≤ VCTRL ≤ 1.35 V, the current-sense threshold smoothly transitions from the linear function of VCTRL to the 100 mV constant value. Tie CTRL to VREF for the 100 mV full scale threshold. Force the pin below 0.3 V to stop switching. 11 ISP Positive Terminal of the ISP/ISN Current-Sense Resistor (RIS). Ensure accurate current sense with Kelvin connection. 12 ISN Negative Terminal of the ISP/ISN Current-Sense Resistor (RIS). Ensure accurate current sense with Kelvin connection. 13 ISMON ISP/ISN Current-Sense Monitor Output. The ISMON pin generates a voltage equal to ten times V(ISP-ISN) plus 0.25 V offset voltage. For parallel applications, tie the master ADPL76030 ISMON pin to the slave ADPL76030 CTRL pin. 14 PGOOD Power Good Open Drain Output. The PGOOD pin is pulled low when the FB pin is within ±10% of the final regulation voltage. To function, the pin requires an external pull-up resistor. 15 SS Soft-Start Timer Setting. The SS pin is used to set the soft-start timer by connecting a capacitor to ground. An internal 12.5 µA pull-up current charging the external SS capacitor gradually ramps up FB regulation voltage. A 22 nF capacitor is recommended on this pin. Any UVLO or thermal shutdown immediately pulls the SS pin to ground and stops switching. Using a single resistor from SS to VREF, the ADPL76030 can be set in three different fault protection modes during output short-circuit condition: hiccup (no resistor), latch-off (499 kΩ), and keep-running (100 kΩ). See more details in the Applications Information section. 16 FB Voltage Loop Feedback Input. The FB pin is used for constant-voltage regulation and output fault protection. The internal error amplifier with its output VC regulates VFB to 1.00 V through the DC/DC converter. During output short-circuit (VFB < 0.25 V) condition, the part gets into one fault mode per customer setting. During an overvoltage (VFB > 1.1V) condition, the part turns off all TG1, BG1, TG2, and BG2. 17 VC Error Amplifier Output to Set Inductor Current Comparator Threshold. The VC pin is used to compensate the control loop with an external RC network. 18 RT Switching Frequency Setting. Connect a resistor from this pin to ground to set the internal oscillator frequency from 600 kHz to 1.4 MHz. 19 SYNC/SPRD Switching Frequency Synchronization or Spread Spectrum. Ground this pin for switching at internal oscillator frequency. Apply a clock signal for external frequency |
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