PM7341 datasheet(27/413 Pages) PMC

27 / 413 page

PRELIMINARY

INVERSE MULTIPLEXING OVER ATM

PM7341 S/UNI-IMA-84

DATASHEET

PMC-2000223

ISSUE 4

INVERSE MULTIPLEXING OVER ATM

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

• Interfaces to a 1M x 16 ( for at least 69 msec of T1, 56 msec of E1 differential

delay tolerance)or 4M x 16 SDRAM ( for 279 msec of T1, 226 msec of E1

differential delay tolerance) through a 16-bit SDRAM interface.

• Provides a 16-bit microprocessor bus interface for configuration and Link and

Unit Management.

• ATM receive interface supports 8- and 16-bit UTOPIA L2 or Any-PHY cell

interfaces at clock rates up to 52 MHz.

• Any-PHY receive slave appears as single device. The PHY-ID of each cell

is identified in the in-band address.

• UTOPIA L2 receive slave appears as a 31 port multi-PHY.

• UTOPIA L2 receive slave can also appear as a single port with the logical

port provided as a prepend or in the HEC/UDF field.

• ATM transmit interface supports 8- and 16-bit UTOPIA L2 and Any-PHY cell

interfaces at clock rates up to 52 MHz.

• Each link configured for cell delineation or each IMA group appears as a

PHY port on the Any-PHY and UTOPIA L2 bus.

• Any-PHY transmit slave appears as an 84-port multi-PHY. The PHY-ID of

each cell is identified in the in-band address.

• UTOPIA L2 transmit slave appears as a 31-port multi-PHY.

• Seamlessly interconnects to PMC-Sierra’s PM7326 S/UNI-APEX ATM/Packet

Traffic Manager and Switch and PM7324 S/UNI-ATLAS ATM layer devices.

Loopback and Diagnostic Features

• Supports UTOPIA L2 / Any-PHY Loopback (global loopback– where all cells

received on the UTOPIA L2 / Any-PHY interface are looped back out)

• Supports Line Side Loopback (global loopback– where all data received on

the line side is looped back out)

PM7341 Datasheet(PDF) 27 Page - PMC-Sierra, Inc