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PM7341 Datasheet(PDF) 47 Page - PMC-Sierra, Inc |
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PM7341 Datasheet(HTML) 47 Page - PMC-Sierra, Inc |
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47 / 413 page ![]() PRELIMINARY INVERSE MULTIPLEXING OVER ATM PM7341 S/UNI-IMA-84 DATASHEET PMC-2000223 ISSUE 4 INVERSE MULTIPLEXING OVER ATM PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 49 9.4 Transmit Slave Interface (UTOPIA L2 mode) (26 Signals) Pin Name Type Pin No. Function TCLK Input F25 The Transmit Clock (TCLK) signal is used to transfer cells across the ANY-PHY interface to the internal downstream cell buffers. The TCA output is updated on the rising edge of TCLK. The TENB, TSOC, TDAT[15:0], TPRTY, TADR[4:0] inputs are sampled on the rising edge of TCLK. The TCLK input must cycle at a 52 MHz or lower instantaneous rate. TCA Tristate Output N26 The Transmit Cell Available (TCA) is an active high signal that indicates the availability of space in the selected logical channel FIFO when polled using the TADR[4:0] signals. The S/UNI-IMA-84 drives TCA with the cell space availability status for the polled port on TCLK cycles after a valid TADR[4:0} address is sampled. The TCA output is high-impedance when not polled. The TCA output is updated on the rising edge of TCLK. TENB Input P24 The Transmit enable bar (TENB) is an active low signal that is used to indicate cell transfers to the internal cell buffers. The TENB input is sampled on the rising edge of TCLK. TADR[4] TADR[3] TADR[2] TADR[1] TADR[0] Input M23 K25 L24 K26 K23 The Transmit Address (TADR[4:0]) signals are used to address logical channels for the purposes of polling and device selection. The TADR[4:0] input bus is sampled on the rising edge of TCLK. |
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