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PM7341 Datasheet(PDF) 60 Page - PMC-Sierra, Inc

Part # PM7341
Description  S/UNI INVERSE MULTIPLEXING FOR ATM, 84 LINKS
PDF  413 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7341 Datasheet(HTML) 60 Page - PMC-Sierra, Inc

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PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7341 S/UNI-IMA-84
DATASHEET
PMC-2000223
ISSUE 4
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
62
Pin Name
Type
Pin
No.
Function
DV5
Input
T1
The Active High Drop Bus Payload Indicator
(DV5) is an active high signal that locates the
position of the floating payloads for each tributary
within the SBI BUS structure. Timing differences
between the port timing and the SBI BUS timing are
indicated by adjustments of this payload pointer
relative to the fixed SBI BUS structure.
Multiple PHY-devices can drive this signal at
uniquely assigned tributary columns within the SBI
BUS structure. All movements indicated by this
signal must be accompanied by appropriate
adjustments in the DPL signal.
The DV5 input signal is sampled on the rising edge
of REFCLK.
AC1FP
Input
R2
The Active High Add Bus C1 Frame Pulse (C1FP)
signal is externally generated to indicate the first C1
octet of each four-frame SBI multiframe on the Add
bus.
This frame pulse is a single REFCLK cycle long and
is sampled on the rising edge of REFCLK.
This signal should be pulsed once every fourth C1
octet to produce a 2 KHz multiframe signal. The
frame pulse does not need to be repeated every
fourth SBI frame. The S/UNI-IMA-84 will synchronize
to this signal and flywheel in its absence.
ADATA[7]
ADATA[6]
ADATA[5]
ADATA[4]
ADATA[3]
ADATA[2]
ADATA[1]
ADATA[0]
Tristate
Output
M2
M1
L3
N2
M4
N1
M3
P2
The Add Data (ADATA[7:0]) signals are a time
division multiplexed bus which transports tributaries
by assigning them to fixed octets within the SBI BUS
structure.
The S/UNI-IMA-84 drives ADATA[7:0] only at
uniquely assigned tributary columns within the SBI
BUS structure.
The ADATA[7:0] output signals are updated on the
rising edge of REFCLK.



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