PM7341 datasheet(64/413 Pages) PMC

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PRELIMINARY

INVERSE MULTIPLEXING OVER ATM

PM7341 S/UNI-IMA-84

DATASHEET

PMC-2000223

ISSUE 4

INVERSE MULTIPLEXING OVER ATM

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Pin Name

Type Pin

No.

Function

Input

AF22

The Output Enable (OE) is an active high signal

that allows all of the outputs of the device to operate

in their functional state. When this signal is low, all

outputs of the S/UNI-IMA-84 go to the high

impedance state, with the exception of TDO.

SYSCLK

Input

AE10

The System Clock (SYSCLK) signal is the master

clock for the S/UNI-IMA-84 device. The core S/UNI-

IMA-84 logic (including the SDRAM interface) is

timed to this signal.

External SDRAM devices share this clock and must

have clocks aligned within 0.2ns skew of the clock

seen by the S/UNI-IMA-84 device.

This clock must be stable prior to deasserting RSTB

0->1.

SYSCLK must cycle at a 50-55 MHz instantaneous

rate to support the maximum number of links (84 T1,

63 E1 or 3 DS3).

REFCLK

Input

SBI_MODE:The Reference Clock (REFCLK) signal

is an externally generated 19.44MHz +/-50ppm

clock with a nominal 50% duty cycle. REFCLK is

common to both the add and drop sides of the SBI

BUS.

In CLK/Data mode, REFCLK is required and may be

operated at frequencies up to 52 MHz. In general,

for T1 and E1 links, 33 MHz is sufficient. See

12.3.2.3 for details on selecting the proper

frequency.

AD22

No Connect. This signal ball is not connected to the

die.

PM7341 Datasheet(PDF) 64 Page - PMC-Sierra, Inc

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