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PM73487 Datasheet(PDF) 26 Page - PMC-Sierra, Inc |
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PM73487 Datasheet(HTML) 26 Page - PMC-Sierra, Inc |
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26 / 251 page ![]() PM73487 QRT PMC-Sierra, Inc. PMC-980618 Issue 3 622 Mbps ATM Traffic Management Device Released Datasheet 14 2 THEORY OF OPERATIONS 2.1 Overview The QRT is a 622 Mbps, full duplex, intelligent routing table which, when used with a switch fab- ric composed of either SE or QSE devices, can implement ATM switches from 622 Mbps to 160 Gbps. The QRT supports a 16-bit UTOPIA Level 2 interface for ease of connection to PHY or AAL layer devices. Four nibble-wide data interfaces connect the QRT to the switch interface. External DRAM memory devices provide receive and transmit cell buffering, and external SRAM devices provide control data for the QRT. This section explains the algorithms for the data flow. Figure 14 shows an overview of the QRT system. 2.2 Interface Descriptions 2.2.1 Switch Fabric Interface The QRT switch fabric interface consists of four groups of signals from both the ingress (receive side) and the egress (transmit side). Each group consists of a Start-Of-Cell (SE_SOC_OUT) sig- nal, a nibble-wide data bus, and a backpressure acknowledgment (BP_ACK_IN) signal. The Start-Of-Cell (SE_SOC_OUT) signal is transmitted at the ingress at the same time as the begin- ning of a cell. SE_SOC_OUT on the ingress is common to all four groups. The BP_ACK_OUT signal flows from the egress through the switch fabric, in the direction opposite the data, and indi- cates whether a cell has successfully passed through the switch fabric. Other signals associated with the switch fabric interface are the switch element clock (SE_CLK) and RX_CELL_START. To support the highest possible throughput for various switch fabric configurations, a clock speed-up factor of 1.6 is used. That is, the switch fabric is run at a rate that is effectively 1.6 times faster than the line rate. Figure 14. QRT System Overview QRT (PM73487) Receive Cell SDRAM Transmit Cell SDRAM Control SSRAM Receive UTOPIA Level 2 Interface Transmit UTOPIA Level 2 Interface To QSE Host Interface From QSE |
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