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PM73487 Datasheet(PDF) 91 Page - PMC-Sierra, Inc |
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PM73487 Datasheet(HTML) 91 Page - PMC-Sierra, Inc |
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91 / 251 page  PM73487 QRT PMC-Sierra, Inc. PMC-980618 Issue 3 622 Mbps ATM Traffic Management Device Released Datasheet 79 6.2 DRAM External Memory Timing NOTE: All inputs are the minimum required. All outputs are the minimum expected. All inputs and outputs are assume to have a 30 pf capacitive loading. The RX_DRAM_CLK and TX_DRAM_CLK are assume to have a 22 ohm series terminated resister connected to a combined capacitive load of 36 pf. Figure 52 shows the receive DRAM external memory 100 MHz read timing. Figure 52. Receive DRAM External Memory 100 MHz Read Timing Symbol Parameter Signals Min Max Unit Tcyc Clock period RX_DRAM_CLK 10 ns Tch Clock high period RX_DRAM_CLK 3 ns Tcl Clock low period RX_DRAM_CLK 3 ns Taddrsu Address setup time RX_DRAM_ADD(8:0) 2.7 ns Tbasu Bank address setup time RX_DRAM_BA 2.9 ns Taddrh Address hold time RX_DRAM_ADD(8:0) 1.3 ns Tbah Bank address hold time RX_DRAM_BA 1.5 ns Tckh Enable hold time * DRAM_CKE ns Tcksu Enable setup time * DRAM_CKE ns Trassu RAS setup time /RX_DRAM_RAS 3.1 ns Trash RAS hold time /RX_DRAM_RAS 1.5 ns Tcassu CAS setup time /RX_DRAM_CAS 3.2 ns Tcash CAS hold time /RX_DRAM_CAS 1.5 ns Tcssu Chip select setup time /RX_DRAM_CS(1:0) 2.4 ns Tcsh Chip select hold time /RX_DRAM_CS(1:0) 2.2 ns Trdh Required hold time required (read data) RX_DRAM_DATA(31:0) 2.7 ns Tcyc Tcyc Tch Tcl Tch Tcl Tcksu Tckh Tcssu Tcsh Trassu Trash Tcassu Tcash Taddrsu Taddrh Twesu Tweh Trds Trdh Tbasu Tbah ROW COLUMN VALID DATA RX_DRAM_CLK DRAM_CKE /RX_DRAM_CS(1:0) /RX_DRAM_RAS /RX_DRAM_CAS RX_DRAM_ADD(8:0) /RX_DRAM_WE RX_DRAM_DATA(31:0) RX_DRAM_BA |
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