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PM73487 Datasheet(PDF) 77 Page - PMC-Sierra, Inc

Part # PM73487
Description  622 Mbps ATM Traffic Management Device
PDF  251 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM73487 Datasheet(HTML) 77 Page - PMC-Sierra, Inc

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PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
Released
Datasheet
65
4.3.3
Switch Element Interface Signals
Table 10. Switch Element Interface Signals (47 Pins)
Signal Name
Ball
Type
Drive/
Input Level
Slew
Rate
Description
SE_CLK
AA26
In
CMOS
Switch Element Clock is the 50 MHz or
66 MHz clock for nibble transfer.
RX_CELL_START
W28
In
5 V or LV
TTL
Receive Cell Start indicates the SOC time in
the receive direction. It should be driven high
every cell time (118 SE_CLKs).
BP_ACK_IN(3:0)
R27, U29,
U28, T28
In
5 V or LV
TTL
Backpressure Input 3 down to 0. It carries the
cell acknowledge and backpressure from the
switch fabric.
SE_SOC_OUT
L27
Out
8 ma
Mod
Switch Fabric Start Of Cell Out indicates the
SOC for all four SE_D_OUT signals. This sig-
nal precedes the first nibble of cell by one
clock. For cells leaving the QRT and entering
the switch fabric, this signal indicates the SOC.
SE_D_OUT0(3:0)
P25, R28,
R25, R26
Out
5 ma
Mod
Switch Element Data Out Ports 3 down to 0
Bits 3 down to 0 are four nibble-wide pathways
that carry the cell to the QSEs (PM73488).
SE_D_OUT1(3:0)
N28, P28,
P26, P27
Out
5 ma
Mod
SE_D_OUT2(3:0)
N27, M26,
N29, M27
Out
5 ma
Mod
SE_D_OUT3(3:0)
L26, N26,
M28, L28
Out
5 ma
Mod
BP_ACK_OUT(3:0)
U27, T27,
U26, V28
Out
8 ma
Mod
Backpressure Output 3 down to 0 asserts mul-
tipriority backpressure and cell acknowledge
toward the switch fabric.
SE_SOC_IN(3:0)
V26, T25,
V25, U25
In
5 V or LV
TTL
Switch Fabric Start of Cell 3 to 0 indicates the
SOC time in the transmit direction for the four
incoming SE_D_IN3, SE_D_IN2, SE_D_IN1
and SE_D_IN0, respectively.
SE_D_IN0(3:0)
AB26, AA25,
AC28, AD28
In
5 V or LV
TTL
Switch Element Data In Ports 3 to 0 Bits 3
down to 0 are part of the nibble-wide, 50 MHz
data pathway that carries the cell from the
switch fabric.
SE_D_IN1(3:0)
AB27, Y26,
AD29, AB28
In
5 V or LV
TTL
SE_D_IN2(3:0)
W26, Y25,
Y27, W25
In
5 V or LV
TTL
SE_D_IN3(3:0)
W27, AA28,
AA27, Y28
In
5 V or LV
TTL



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