PM73487 datasheet(80/251 Pages) PMC

80 / 251 page

PM73487 QRT

PMC-Sierra, Inc.

PMC-980618

Issue 3

622 Mbps ATM Traffic Management Device

Released

Datasheet

4.3.6

ABR_RAM Interface Signals

Table 13. ABR_RAM Interface Signals (22 Pins)

Signal Name

Ball

Type

Drive/

Input Level

Slew

Rate

Description

ABR_RAM_AD(16:0)

G2, J5, H4, F2, E2,

G3, H5, F3, G4,

D2, E3, F4, C2,

F5, D3, G5, E4

Bidir

5 ma/CMOS

Mod

ABR RAM Address Data Bits 16 to 0 form the

time division multiplexed address data bus.

ABR_RAM_CLK

Out

8 ma

Fast

ABR RAM Clock provides the clock to the AB

RAM.This signal should be terminated with a

series resistor before connecting to the RAM

modules

/ABR_RAM_ADSP

Out

5 ma

Mod

ABR RAM Address Data Selection defines the

type of information on the address/data bus

(ADDRDATA(31:0)).

/ABR_RAM_OE

Out

8 ma

Fast

ABR_RAM Output Enable is an active low sig-

nal that enables the RAM to drive

ABR_RAM_AD(16:0).This signal should be

terminated with a series resistor before con-

necting to the RAM modules

/ABR_RAM_ADV

Out

5 ma

Mod

ABR_RAM Advance is an active low signal

that signals the external SSRAM to advance

its address.

/ABR_RAM_WE

Out

5 ma

Mod

ABR RAM Write Enable is an active low signal

that enables a write into the ABR_RAM.

PM73487 Datasheet(PDF) 80 Page - PMC-Sierra, Inc

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