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PM73487 Datasheet(PDF) 94 Page - PMC-Sierra, Inc

Part # PM73487
Description  622 Mbps ATM Traffic Management Device
PDF  251 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM73487 Datasheet(HTML) 94 Page - PMC-Sierra, Inc

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PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
Released
Datasheet
82
Figure 55 shows the transmit DRAM external memory 100 MHz write timing.
Tcksu
Clock enable setup time
DRAM_CKE
*
ns
Trassu
RAS setup time
/TX_DRAM_RAS
3.3
ns
Trash
RAS hold time
/TX_DRAM_RAS
1.5
ns
Tcassu
CAS setup time
/TX_DRAM_CAS
3.3
ns
Tcash
CAS hold time
/TX_DRAM_CAS
1.5
ns
Tcssu
Chip select setup time
/TX_DRAM_CS(1:0)
2.7
ns
Tcsh
Chips select hold time
/TX_DRAM_CS(1:0)
1.5
ns
Trdh
(Read) Data Valid required after clock
TX_DRAM_DATA(31:0)
2
ns
Twesu
Write enable setup time
/TX_DRAM_WE
2.9
ns
Tweh
Write enable hold time
/TX_DRAM_WE
1.5
ns
Trds
(Read) Data valid required before clock
TX_DRAM_DATA(31:0)
0
ns
Figure 55. Transmit DRAM External Memory 100 MHz Write Timing
Symbol
Parameter
Signals
Min
Max
Unit
Tcyc
TX_DRAM_CLK period
TX_DRAM_CLK
10
ns
Tch
TX_DRAM_CLK high period
TX_DRAM_CLK
3
ns
Tcl
TX_DRAM_CLK low period
TX_DRAM_CLK
3
ns
Taddrsu
Address setup time
TX_DRAM_ADD(8:0)
3.1
ns
Taddrh
Address hold time
TX_DRAM_ADD(8:0)
1.3
ns
Tbasu
Bank address setup time
TX_DRAM_BA
2.8
ns
Tbah
Bank address hold time
TX_DRAM_BA
1.5
ns
Symbol
Parameter
Signals
Min
Max
Unit
12
34
56
7
8
Tcyc
Tcyc
Tch
Tcl
Tch
Tcl
Tcksu
Tckh
Tcssu
Tcsh
Trassu
Trash
Tcassu
Tcash
Taddrsu
Taddrh
Twesu
Tweh
Tdsu
Tdh
Tbasu
Tbah
ROW
COLUMN
VALID DATA
VALID DATA
VALID DATA
VALID DATA
TX_DRAM_CLK
DRAM_CKE
/TX_DRAM_CS(1:0)
/TX_DRAM_RAS
/TX_DRAM_CAS
TX_DRAM_ADD(8:0)
/TX_DRAM_WE
TX_DRAM_DATA(31:0)
TX_DRAM_BA



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