PM73487 datasheet(85/251 Pages) PMC

85 / 251 page

PM73487 QRT

PMC-Sierra, Inc.

PMC-980618

Issue 3

622 Mbps ATM Traffic Management Device

Released

Datasheet

4.3.10

Boundary Scan Signals

Table 18. Test Signals (8 Signal Pins)

Signal Name

Ball

Type

Drive/Input

Level

Slew

Rate

Description

/JTAG_RESET

CMOS

JTAG Reset is an active low, true asynchronous reset to the

JTAG controller.

JTAG_TCK

CMOS

Scan Test Clock is an independent clock used to drive the inter-

nal boundary scan test logic. Connect this signal to VDD

through a pull-up resistor.

JTAG_TDI

CMOS

Scan Test Data Input is the serial input for boundary scan test

data and instruction bits. Connect this signal to VDD through a

pull-up resistor.

JTAG_TDO

Out

4 ma

Mod

Scan Test Data Output is the serial output for boundary scan

test data.

JTAG_TMS

CMOS

Scan Test Mode Select controls the operation of the boundary

scan test logic. Connect this signal to VDD through a pull-up

resistor.

/TEST_MODE

CMOS

This is a manufacturing test mode bit for manufacturing test. It

MUST be pulled up for functional mode on the board.

/SCAN_EN

CMOS

Scan Test Enable is used to enable the internal scan test logic.

Connect this signal to VDD through a pull-up resistor.

PROC_MON

T26

Out

N/A

Process Monitor is used for manufacturing test. It is connected

to a NAND tree that may be used for VIL/VIH testing.

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