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PM73487 Datasheet(PDF) 76 Page - PMC-Sierra, Inc

Part # PM73487
Description  622 Mbps ATM Traffic Management Device
PDF  251 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM73487 Datasheet(HTML) 76 Page - PMC-Sierra, Inc

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PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
Released
Datasheet
64
4.3.1
Processor Interface Signals
4.3.2
Statistics Interface Signal
Table 8. Processor Interface Signals (38 Pins)
Signal Name
Ball
Type
Drive/
Input Level
Slew
Rate
Description
PCLK
C6
In
CMOS
Processor Clock
ADDRDATA(31:0)
B8, B7, D9, C8, D8,
E10, C10, E9, D10,
B10, C9, B9, C11,
E12, E11, E13, D11,
C12, D13, B11, B12,
D12, C13, B13, C14,
A13, B14, C15, D14,
E14, B15, E15
Bidir
5 ma/ 5 V or
LV TTL
Mod-
erate
(Mod)
Address/Data Bits 31 to 0 are part of the
32-bit processor address/data bus.
/ADS
C7
In
5 V or LV
TTL
Address/Data Status is an active low sig-
nal that indicates an address state.
W_/RD
E8
In
5 V or LV
TTL
Write_/Read is an active high signal that
selects a write cycle when it is high.
/READY
D7
Out
5 ma
Mod
Ready is an active low signal that indi-
cates the processor cycle is finished.
When this signal is deasserted, it is driven
high, then tristated.
/CS
A6
In
5 V or LV
TTL
Chip Select is an active low signal that
selects the device for processor access.
/INTR
B6
Out
5 ma
Mod
Interrupt is an active low signal that indi-
cates an interrupt is present.
Table 9. Statistics Interface Signal (1 Pin)
Signal Name
Ball
Type
Drive/
Input Level
Slew
Rate
Description
STATS_STRB
D6
Out
8 ma
Mod
STATS_STRB is an active high signal that indicates a fixed
position in the cell time in the SYS_CLK domain. This can be
used to trigger external circuitry.



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