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PM73487 Datasheet(PDF) 95 Page - PMC-Sierra, Inc

Part # PM73487
Description  622 Mbps ATM Traffic Management Device
PDF  251 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM73487 Datasheet(HTML) 95 Page - PMC-Sierra, Inc

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PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
Released
Datasheet
83
* The DRAM_CKE is a functionally static signal. Software should ensure that the DRAM_CKE
is set at least 1 microsecond before desserting the SW_RESET bit.
6.3
SRAM Timings
All inputs and outputs are assume to have a 30 pf capacitive loading. The ALRAM_CLK,
ABRAM_CLK and CHRAM_CLK are assume to have a 22 ohm series terminated resister
connected to a combined capacitive load of 36 pf.
Figure 56 shows the AL RAM read timing.
Tckh
CLK enable hold time
DRAM_CKE
*
ns
Tcksu
CLK enable setup time
DRAM_CKE
*
ns
Trassu
RAS setup time
/TX_DRAM_RAS
3.3
ns
Trash
RAS hold time
/TX_DRAM_RAS
1.5
ns
Tcassu
CAS setup time
/TX_DRAM_CAS
3.3
ns
Tcash
CAS hold time
/TX_DRAM_CAS
1.5
ns
Tcssu
Chip select setup time
/TX_DRAM_CS(1:0)
2.7
ns
Tcsh
Chip select hold time
/TX_DRAM_CS(1:0)
1.5
ns
Twesu
Write enable setup time
/TX_DRAM_WE
2.9
ns
Tweh
Write enable hold time
/TX_DRAM_WE
1.5
ns
Tdsu
(Write) Data valid before clock
TX_DRAM_DATA(31:0)
2.2
ns
Tdh
(Write) Data Valid after clock
TX_DRAM_DATA(31:0)
1.5
ns
Figure 56. Address Lookup RAM Read Timing
Symbol
Parameter
Signals
Min
Max
Unit
1
2
3
4
5
Tcyc
Tcyc
Tch
Tcl
Tch
Tcl
Tadss
Tadh
Toesu
Toeh
Tadrsu
Tadrh
Tadrsu
Tadh
Tadrsu
Tadrh
Twesu
Tweh
Trds
Trdh
VALID DATA
ALRAM READ CYCLE
ALRAM_CLK
/ALRAM_ADSC
/ALRAM_OE
ALRAM_ADD(18:0)
ALRAMADD17N
ALRAMADD18N
/ALRAM_WE
ALRAM_DATA(16:0)



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