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PM7375-SC Datasheet(PDF) 142 Page - PMC-Sierra, Inc

Part # PM7375-SC
Description  LOCAL ATM SAR & PHYSICAL LAYER
PDF  430 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7375-SC Datasheet(HTML) 142 Page - PMC-Sierra, Inc

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PM7375 LASAR-155
DATA SHEET
PMC-931127
ISSUE 6
LOCAL ATM SAR & PHYSICAL LAYER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
126
10.1.16
Register 0x19 (0x064): RLOP Interrupt Enable/Status
Bit
Type
Function
Default
Bit 15
Unused
X
Bit 14
Unused
X
Bit 13
Unused
X
Bit 12
Unused
X
Bit 11
Unused
X
Bit 10
Unused
X
Bit 9
Unused
X
Bit 8
Unused
X
Bit 7
R/W
FEBEE
0
Bit 6
R/W
BIPEE
0
Bit 5
R/W
LAISE
0
Bit 4
R/W
FERFE
0
Bit 3
R
FEBEI
X
Bit 2
R
BIPEI
X
Bit 1
R
LAISI
X
Bit 0
R
FERFI
X
FERFI:
The FERFI bit is the far end receive failure interrupt status bit. FERFI is set high
when a change in the line FERF state occurs. This bit is cleared when this
register is read.
LAISI:
The LAISI bit is the line AIS interrupt status bit. LAISI is set high when a change
in the line AIS state occurs. This bit is cleared when this register is read.
BIPEI:
The BIPEI bit is the line BIP-8/24 interrupt status bit. BIPEI is set high when a
line layer (B2) bit error is detected. This bit is cleared when this register is read.
FEBEI:
The FEBEI bit is the line far end block error interrupt status bit. FEBEI is set high
when a line layer FEBE (Z2) is detected. This bit is cleared when this register is
read.
FERFE:
The FERFE bit is an interrupt enable for the far end receive failure alarm. When



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