CYRF69103
Document #: 001-07611 Rev *B
Page 52 of 73
Mnemonic
RX_STATUS_ADR
Address
0x08
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
1
-
-
-
Read/Write
R
R
R
R
R
R
R
R
Function
RX ACK
PKT ERR
EOP ERR
CRC0
Bad CRC
RX Code
RX Data Mode
It is expected that firmware does not read this register until after TX GO self clears. Status bits are non-atomic (different flags may change value
at different times in response to a single event).
Bit 7
RX Packet Type. This bit is set when the received packet is an ACK packet, and cleared when the received packet is a standard
packet.
Bit 6
Receive Packet Type Error. This bit is set when the packet type received is what not was expected and cleared when the
packet type received was as expected. For example, if a data packet is expected and an ACK is received, this bit will be set.
Bit 5
Unexpected EOP. This bit is set when an EOP is detected before the expected data length and CRC16 fields have been
received. This bit is cleared when SOP pattern for the next packet has been received. This includes the case where there are
invalid bits detected in the length field and the length field is forced to 0.
Bit 4
Zero-seed CRC16. This bit is set whenever the CRC16 of the last received packet has a zero seed.
Bit 3
Bad CRC16. This bit is set when the CRC16 of the last received packet is incorrect.
Bit 2
Receive Code Length. This bit indicates the DATA_CODE_ADR code length used in the last correctly received packet.
1 = 64-chip code, 0 = 32-chip code.
Bits 1:0
Receive Data Mode. These bits indicate the data mode of the last correctly received packet. 00 = 1-Mbps GFSK, 01 = 8DR,
10 = DDR, 11 = Not Valid. These bits do not apply to unframed packets.
Mnemonic
RX_COUNT_ADR
Address
0x09
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Function
RX Count
Count bits are non-atomic (updated at different times).
Bits 7:0
This register contains the total number of payload bytes received during reception of the current packet. After packet reception
is complete, this register will match the value in RX_LENGTH_ADR unless there was a packet error. This register is reset to
0x00 when RX_LENGTH_ADR is loaded. Count should not be read when RX_GO = 1 during a transaction.
Mnemonic
RX_LENGTH_ADR
Address
0x0A
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Function
RX Length
Length bits are non-atomic (different flags may change value at different times in response to a single event).
Bits 7:0
This register contains the length field, which is updated with the reception of a new length field (shortly after start of packet
detected). If there is an error in the received length field, 0x00 is loaded instead, except when using GFSK datarate, and an
error is flagged.
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