CYRF69103
Document #: 001-07611 Rev *B
Page 27 of 73
Figure 12. Sleep Timing
Wakeup Sequence
Once asleep, the only event that can wake the system up is
an interrupt. The global interrupt enable of the CPU flag
register does not need to be set. Any unmasked interrupt will
wake the system up. It is optional for the CPU to actually take
the interrupt after the wakeup sequence. The wakeup
sequence is synchronized to the 32-KHz clock for purposes of
sequencing a startup delay, to allow the Flash memory module
enough time to power up before the CPU asserts the first read
access. Another reason for the delay is to allow the oscillator,
Bandgap, and LVD/POR circuits time to settle before actually
being used in the system. As shown in Figure 13, the wake p
sequence is as follows:
1. The wakeup interrupt occurs and is synchronized by the
negative edge of the 32-KHz clock.
2. At the following positive edge of the 32-KHz clock, the
system-wide PD signal is negated. The Flash memory
module, internal oscillator, EFTB, and bandgap circuit are
all powered up to a normal operating state.
3. At the following positive edge of the 32-KHz clock, the
current values for the precision POR and LVD have settled
and are sampled.
4. At the following negative edge of the 32-KHz clock (after
about 15 µs nominal), the BRQ signal is negated by the
sleep logic circuit. On the following CPUCLK, BRA is
negated by the CPU and instruction execution resumes.
Note that in Figure 13 fixed function blocks, such as Flash,
internal oscillator, EFTB, and bandgap, have about 15 µs
start up. The wakeup times (interrupt to CPU operational)
will range from 75 µs to 105 µs.
Firmware write to SCR
SLEEP bit causes an
immediate BRQ
IOW
SLEEP
BRQ
PD
BRA
CPUCLK
CPU captures
BRQ on next
CPUCLK edge
CPU
responds
with a BRA
On the falling edge of
CPUCLK, PD is asserted.
The 24/48 MHz system clock
is halted; the Flash and
bandgap are powered down
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