CYRF69103
Document #: 001-07611 Rev *B
Page 59 of 73
Mnemonic
MODE_OVERRIDE_ADR
Address
0x1D
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
-
-
0
Read/Write
W
W
W
W
W
-
-
W
Function
RSVD
RSVD
FRC SEN
FRC AWAKE
Not Used
Not Used
RST
Bits 7
Reserved. Do not write a 1 to these bits.
Bits 5
Manually Initiate Synthesizer. Setting this bit forces the synthesizer to start. Clearing this bit has no effect. For this bit to operate
correctly, the oscillator must be running before this bit is set.
Bits 4:3
Force Awake. Force the device out of sleep mode. Setting both bits of this field forces the oscillator to keep running at all times
regardless of the END STATE setting. Clearing both of these bits disables this function.
Bits 0
Reset. Setting this bit forces a full reset of the device. Clearing this bit has no effect.
Mnemonic
RX_OVERRIDE_ADR
Address
0x1E
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
-
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
Function
ACK RX
RXTX DLY
MAN RXACK
FRC RXDR
DIS CRC0
DIS RXCRC
ACE
Not Used
This register provides the ability to override some automatic features of the device.
Bits 7
When this bit is set, the device uses the transmit synthesizer frequency rather than the receive synthesizer frequency for the
given channel when automatically entering receive mode.
Bits 6
When this bit is set and ACK EN is enabled, the transmission of the ACK packet is delayed by 20
µs.
Bits 5
Force Expected Packet Type. When this bit is set, and the device is in receive mode, the device is configured to receive an
ACK packet at the data rate defined in TX_CFG_ADR.
Bits 4
Force Receive Data Rate. When this bit is set, the receiver will ignore the data rate encoded in the SOP symbol, and will
receive data at the data rate defined in TX_CFG_ADR.
Bits 3
Reject packets with a zero-seed CRC16. Setting this bit causes the receiver to reject packets with a zero-seed, and accept only
packets with a CRC16 that matches the seed in CRC_SEED_LSB_ADR and CRC_SEED_MSB_ADR.
Bits 2
The RX CRC16 checker is disabled. If packets with CRC16 enabled are received, the CRC16 will be treated as payload data
and stored in the receive buffer.
Bits 1
Accept Bad CRC16. Setting this bit causes the receiver to accept packets with a CRC16 that do not match the seed in
CRC_SEED_LSB_ADR and CRC_SEED_MSB_ADR. An ACK is to be sent regardless of the condition of the received CRC16.
Mnemonic
TX_OVERRIDE_ADR
Address
0x1F
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
ACK TX
FRC PRE
RSVD
MAN TXACK
OVRD ACK
DIS TXCRC
RSVD
TX INV
This register provides the ability to override some automatic features of the device.
Bits 7
When this bit is set, the device uses the receive synthesizer frequency rather than the transmit synthesizer frequency for the
given channel when automatically entering transmit mode.
Bits 6
Force Preamble. When this bit is set, the device will transmit a continuous repetition of the preamble pattern (see
PREAMBLE_ADR) after TX GO is set. This mode is useful for some regulatory approval procedures.
Bits 5
Reserved. Do not write a 1 to this bit.
Bits 4
Transmit ACK Packet. When this bit is set, the device sends an ACK packet when TX GO is set.
Bits 3
ACK Override. Use TX_CFG_ADR to determine the data rate and the CRC16 used when transmitting an ACK packet.
Bits 2
Disable Transmit CRC16. When set, no CRC16 field is present at the end of transmitted packets.
Bits 1
Reserved. Do not write a 1 to this bit.
Bits 0
TX Data Invert. When this bit is set the transmit bitstream is inverted.
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