CYRF69103
Document #: 001-07611 Rev *B
Page 64 of 73
Notes
8. It is permissible to connect voltages above VIO to inputs through a series resistor limiting input current to 1 mA. AC timing not guaranteed.
9. Human Body Model (HBM).
10. VREG depends on battery input voltage.
11. Includes current drawn while starting crystal, starting synthesizer, transmitting packet (including SOP and CRC16), changing to receive mode, and receiving
ACK handshake. Device is in sleep except during this transaction.
DC Characteristics (T = 25°C)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
VBAT
Battery Voltage
0–70
°C
1.8
3.6
V
VREG
[10]
PMU Output Voltage
2.7V mode
2.7
2.73
V
VLVD
Low Voltage Detect
LVDCR [2:0] set to 000
VIO
VIO Voltage
1.8
3.6
V
VCC
VCC Voltage
0–70
°C
2.4
3.6
V
Device Current (For total current consumption in different modes, for example Radio, active, MCU, sleep, etc., add Radio
Function Current and MCU Function Current)
ICC (GFSK)
[11]
Average ICC, 1 Mbps, slow channel
PA = 5, 2-way, 4 bytes/10 ms CPU
speed = 6 MHz
9.87
mA
ICC (32-8DR)
[11] Average I
CC, 250 kbps, fast channel
PA = 5, 2-way, 4 bytes/10 ms CPU
speed = 6 MHz
10.2
mA
ISB1
Sleep Mode ICC
VCC = 3.0V, MCU sleep, PMU
disabled
2.72
µA
ISB2
Sleep Mode ICC
VCC = 3.0V, MCU sleep, PMU
enabled
30.4
µA
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