CS4239 datasheet(74/98 Pages) CIRRUS

74 / 98 page

Bus Interface

The ISA bus interface is capable of driving a 24

mA data bus load and therefore does not require

any external data bus buffering. See the Refer-

ence Design Data Sheet for a typical connection

diagram.

Volume Control Interface

Three hardware master volume control pins are

supported: volume up, volume down, and mute.

Hardware volume control is enabled by setting

the VCEN bit in the Hardware Configuration

data, byte 7 (Misc. Config. Byte). Once VCEN

is set, the XTAL1/ACDCS/DOWN pin converts

to the volume down function. The volume con-

trol pins affect the master volume control output

after the analog output mixer. The UP an d

DOWN pins, when low, increment and decre-

ment the master volume. These two pins would

use SPST momentary switches. The MUTE pin

can either be momentary or non-existent where

pressing up and down simultaneously mutes the

output volume. The circuit in Figure 17, contains

optional resistors for EMI and ESD protection;

however, the capacitors are required for switch

debounce.

Pressing the up button, increments the volume.

Pressing the down button, decrements the vol-

ume. Holding either of these buttons in the low

state causes the volume to to continue changing.

The formats are selected using the VCF1 bit in

the Hardware Configuration data, Global Config.

byte.

In the first format, where VCF1 = 0, the mute

function is a momentary switch (similar to up

and down). When MUTE goes low the master

out volume mutes if it was un-muted and vise-

versa (the mute button alternates between mute

and un-mute). If the master volume is muted and

up or down is pressed, the volume automatically

un-mutes.

In the second format, where VCF1 = 1, the

MUTE pin is not used. This is a two-button for-

mat where pressing up and down simultaneously

mutes the master volume. If the master volume

is muted and up or down is individually pressed,

the volume automatically un-mutes.

The two formats listed above as illustrated in

Figure 18.

Crystal / Clock

Two pins have been allocated to allow the inter-

facing of a crystal oscillator: XTALI and

XTALO. The crystal should be designed as fun-

damental mode, parallel resonant, with a load

capacitor of between 10 and 20 pF. The capaci-

tors connected to each of the crystal pins should

be twice the load capacitance specified to the

crystal manufacturer.

An external CMOS clock may be connected to

the crystal input XTALI in lieu of the crystal.

10 nF

DOWN

MUTE

GND

Mute

Down

100 Ω

10 nF

100 Ω

100Ω

Figure 17. Volume Control Circuit

GND

Mute

Down

VCF1 = 0

GND

Mute

Down

VCF1 = 1

Figure 18. Volume Control Formats

DS253PP2

CS4239

CrystalClear Portable ISA Audio System

CS4239 Datasheet(PDF) 74 Page - Cirrus Logic

CS4239 Datasheet(HTML) 74 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

Datasheet Download

Link URL