CS4239 datasheet(33/98 Pages) CIRRUS

33 / 98 page

Capture I/O Data Register

(WSSbase+3, R3, Read Only)

CD7

CD6

CD5

CD4

CD3

CD2

CD1

CD0

CD7-CD0

Capture Data Port. This is the control

during programmed I/O data trans-

fers.

The reading of this register will increment the

state machine so that the following read will be

from the next appropriate byte in the sample.

The exact byte which is next to be read can be

determined by reading the Status register (R2).

Once all relevant bytes have been read, the state

machine will point to the last byte of the sample

until a new sample is received from the ADCs.

Once the Status register (R2) is read and a new

sample is received from the FIFO, the state ma-

chine and Status register (R2) will point to the

first byte of the new sample.

During initialization and software power down

of the WSS Codec, this register can NOT be

written and is always read 10000000 (80h)

Playback I/O Data Register

WSSbase+3, R3, Write Only)

PD7PD6

PD5PD4

PD3PD2

PD1PD0

PD7-PD0

Playback Data Port. This is the

control register where playback data

is written during programmed IO

data transfers.

Writing data to this register will increment the

playback byte tracking state machine so that the

following write will be to the correct byte of the

sample. Once all bytes of a sample have been

written, subsequent byte writes to this port are

ignored. The state machine is reset after the

Status register (R2) is read, and the current sam-

ple is sent to the DACs via the FIFOs.

INDIRECT MAPPED REGISTERS

These registers are accessed by placing the ap-

propriate index in the Index Address register

(R0) and then accessing the Indexed Data regis-

ter (R1). A detailed description of each indirect

be written zero and may be 0 or 1 when read.

Note that indirect registers 16-31 are not avail-

able when in MODE 1 (CMS1,0 in MODE and

ID register I12 are both zero).

Left Analog Loopback (I0)

Default = 000xxxxx

LSS1

LSS0

MGE

res

rbc

MGE

This bit controls the 20 dB gain boost

for the MIC analog input.

LSS1-LSS0

Left output loopback. Setting these

bits to 11 enables the left output

loopback into the input mixer. Bit

combinations of 01, 10, and 00 dis-

able the loopback.

Right Analog Loopback(I1)

Default = 000xxxxx

RSS1

RSS0

MGE

res

rbc

MGE

This bit is identical to the MGE bit in

I0. It controls the 20 dB gain boost

for the MIC analog input.

RSS1-RSS0

Right output loopback. Setting these

bits to 11 enables the right output

loopback into the input mixer. Other

bit combinations disable the loop-

back.

DS253PP2

CS4239

CrystalClear Portable ISA Audio System

CS4239 Datasheet(PDF) 33 Page - Cirrus Logic

CS4239 Datasheet(HTML) 33 Page - Cirrus Logic

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