TMPR3911 datasheet(158/462 Pages) TOSHIBA

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Chapter 5 SIU Module

5-4

5.2.3

Address Decoder Description

Figure 5.2.2 shows a block diagram of the SIM Address Decoder. The Address Decoder generates the

read and write enable pulses for each of the internal TMPR3911/12 control and status registers. The

lower 8 bits of the internal address bus are decoded, along with the SIM chip select and read/write

status signal, to generate any 1 of 256 possible write enable pulses or any 1 of 256 possible read enable

pulses. These enable pulses are used by the circuit/module targeted by the respective read or write pulse

to either latch the data from the CPU (for a write transaction) or to enable the data to the CPU (for a

read transaction). See the next section for a full listing of all the internal function Registers, including

their address offset and read versus write support. The address offset for function Registers is the offset

from the base address ($10C00000) of the function Registers in the System Address Map.

RD MEM CONFIG 0 REG

WR MEM CONFIG 0 REG

ADDR BUS(9:2)

RD/WR

CHIP SELECT

SIM

ADDRESS

DECODER

RD MEM CONFIG 1 REG

WR MEM CONFIG 1 REG

RD MEM CONFIG 2 REG

WR MEM CONFIG 2 REG

RD CHI HOLDING REG

WR CHI HOLDING REG

Figure 5.2.2 SIM Address Decoder Block Diagram

TMPR3911 Datasheet(PDF) 158 Page - Toshiba Semiconductor