TMPR3911 datasheet(157/462 Pages) TOSHIBA

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Chapter 5 SIU Module

5-3

5.2.2

DMA Controller Description

Figure 5.2.1 shows a block diagram of the SIU DMA Controller. The DMA Controller receives the

DMA requests and read/write status from all of the 7 possible DMA sources (Magicbus, video, sound,

telecom, CHI, UARTA, and UARTB) and uses a Priority Encoder to arbitrate and select the highest

priority request. If a new request is received and the DMA controller is currently busy, that request will

remain pending and will be processed as soon as all other higher priority pending requests have been

processed. The priority of the DMA sources and the DMA direction (read or write) supported are shown

in Table 5.2.1.

Table 5.2.1 DMA Sources

DMA Source

priority

DMA read

(from memory)

DMA write

(to memory)

Magicbus

highest

yes

video (burst of 4 longs)

yes

sound

yes

telecom

yes

CHI

yes

UART-A (1 byte)

yes

UART-B (1 byte)

lowest

yes

The state machine for the Priority Encoder also generates the START transaction pulse and read

versus write status signal to the CPU Interface for each DMA transaction. After the arbiter decodes all

received DMA requests and selects the highest priority request as the DMA channel to be processed, the

DMA address and data busses for the selected DMA channel are routed to the memory subsystem. All

DMA sources transfer 1 word per transaction, except for the video which always transfers 4 consecutive

words at a time (and thus returns 4 separate ACKs to the Video Module), and the UARTs which transfer

only 1 byte at a time. The UARTs are thus tagged with the appropriate Byte Enable (corresponding to 1

of 4 byte positions) depending on the byte count in the DMA address counter within the respective

UART Module.

The state machine also generates the required acknowledge (ACK) signal at the end of each DMA

transaction. This ACK signal is used by the circuit corresponding to the respective DMA source to

either latch the data from memory (for a read transaction) or to enable the data to memory (for a write

transaction).

The SIU also contains several test bits (see Section 5.3) which allow detailed testing of the DMA

Controller for various combinations of simultaneous DMA requests. These bits are used for IC testing

and should never be set.

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