TMPR3911 datasheet(153/462 Pages) TOSHIBA

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Chapter 4 BIU Module

4-53

ENRFSH1:

Setting this bit will cause the BIU to begin refreshing Bank 1 DRAMs or SDRAMs. This bit

should not be set until meeting the start up specification requirements for the memory devices.

ENRFSH0:

Setting this bit will cause the BIU to begin refreshing Bank 0 DRAMs or SDRAMs. This bit

should not be set until meeting the start up specification requirements for the memory devices.

RFSHVAL1[5:0]:

These bits define the refresh period for Bank 1 refresh according to the following:

15.26

µs

61.04

µs

91.55

µs

122.07

µs

RFSHVAL0[5:0]:

These bits define the refresh period for Bank 0 refresh according to the following:

15.26

µs

61.04

µs

91.55

µs

122.07

µs

4.7.6

Memory Configuration 5 Register

OFFSET

= $014:

write-only

Bit

Label

RESET

Read/Write

31-9

STARTVAL2[31:9]

8-4

Reserved

3-0

MASK2[3:0]

STARTVAL2[31:9]:

write-only

These bits define the start address for re-map region 2.

MASK2[3:0]:

write-only

These bits define the mask for re-map region 2.

TMPR3911 Datasheet(PDF) 153 Page - Toshiba Semiconductor

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