TMPR3911 datasheet(150/462 Pages) TOSHIBA

150 / 462 page

Chapter 4 BIU Module

4-50

CARD2ACCVAL[3:0]:

These bits define the access time for Card 2 Memory Space.

CARD1ACCVAL[3:0]:

These bits define the access time for Card 1 Memory Space.

CARD2IOACCVAL[3:0]:

These bits define the access time for Card 2 IO and Attribute Space.

CARD1IOACCVAL[3:0]:

These bits define the access time for Card 1 IO and Attribute Space.

ENMCS3PAGE:

Setting this bit will enable Read Page Mode for MCS3.

ENMCS2PAGE:

Setting this bit will enable Read Page Mode for MCS2.

ENMCS1PAGE:

Setting this bit will enable Read Page Mode for MCS1.

ENMCS0PAGE:

Setting this bit will enable Read Page Mode for MCS0.

ENCS3PAGE:

Setting this bit will enable Read Page Mode for CS3.

ENCS2PAGE:

Setting this bit will enable Read Page Mode for CS2.

ENCS1PAGE:

Setting this bit will enable Read Page Mode for CS1.

ENCS0PAGE:

Setting this bit will enable Read Page Mode for CS0.

CARD2WAITEN:

Setting this bit will enable the CARD2WAIT* signal.

CARD1WAITEN:

Setting this bit will enable the CARD1WAIT* signal.

CARD2IOEN:

Setting this bit will cause accesses to Card 2 I/O space to assert the IORD* or IOWR* signals.

This is used for accessing I/O cards. If this bit is not set, RD* or WE* is asserted, which provides

Attribute space access.

TMPR3911 Datasheet(PDF) 150 Page - Toshiba Semiconductor