TMPR3911 datasheet(146/462 Pages) TOSHIBA

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Chapter 4 BIU Module

4-46

ROWSEL1[1:0]:

ROWSEL0[1:0]:

COLSEL1[3:0]:

COLSEL0[3:0]:

These bits determine the Row and Column configuration for addressing according to the

following:

ROW

ROWSEL

COL

COLSEL

18, 17:9

22, 20, 18, 8:1

0000

22, 18, 20, 19, 17:9

19, 18, 8:2

0001

20, 22, 21, 19, 17:9

21, 20, 18, 8:2

0010

22, 23, 21, 19, 17:9

23, 22, 20, 18, 8:2

0011

24, 22, 20, 18, 8:2

0100

18,

φ, X, 8:0

0101

22, X,

φ, 21, 8:0

0110

18,

φ, X, 21, 8:1

0111

22, X,

φ, 23, 21, 8:1

1000

24, 23, 21, 8:2

1001

Reserved

Others

CS3SIZE:

Setting this bit defines CS3 to be a 32-bit port. Otherwise, a 16-bit port is assumed.

CS2SIZE:

Setting this bit defines CS2 to be a 32-bit port. Otherwise, a 16-bit port is assumed.

CS1SIZE:

Setting this bit defines CS1 to be a 32-bit port. Otherwise, a 16-bit port is assumed.

CS0SIZE:

Setting this bit defines CS0 to be a 32-bit port. Otherwise, a 16-bit port is assumed. On RESET,

this signal is set high if the TESTAIU pin is tied high and low if the TESTAIU pin is tied low.

TMPR3911 Datasheet(PDF) 146 Page - Toshiba Semiconductor

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