TMPR3911 datasheet(144/462 Pages) TOSHIBA

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Chapter 4 BIU Module

4-44

4.7

BIU Registers

4.7.1

Memory Configuration 0 Register

OFFSET

= $000:

Bit

Label

RESET

Read/Write

Reserved

ENDCLKOUTTRI

R/W

DISDQMINIT

R/W

ENSDRAMPD

R/W

SHOWDINO

R/W

ENRMAP2

R/W

ENRMAP1

R/W

ENWRINPAGE

R/W

ENCS3USER

R/W

ENCS2USER

R/W

ENCS1USER

R/W

ENCS1DRAM

R/W

19-18

BANK1CONF[1:0]

R/W

17-16

BANK0CONF[1:0]

R/W

15-14

ROWSEL1[1:0]

R/W

13-12

ROWSEL0[1:0]

R/W

11-8

COLSEL1[3:0]

R/W

7-4

COLSEL0[3:0]

R/W

CS3SIZE

R/W

CS2SIZE

R/W

CS1SIZE

R/W

CS0SIZE

See Description

R/W

ENDCLKOUTTRI:

Setting this bit will cause the DCLKOUT pin to tri-state when DGRNT* is asserted during

external bus arbitration. Otherwise, DCLKOUT will continue to operate.

DISDQMINIT:

If this bit is a cleared, the DQMH and DQML signals will go high when coming out of power-

down and remain high until the first access to SDRAM. If this bit is set, this function is disabled

and the DQMH and DQML signals will remain low.

ENSDRAMPD:

Setting this bit will cause the BIU to put the SDRAMs into Power Down mode by lowering

DCKE whenever there are no accesses to the SDRAMs for 7 CLK periods.

SHOWDINO:

Setting this bit will cause internal reads and writes by the processor to function registers to show

externally for debug. The RD* signal provides the read or write status, D[31:0] provide the data,

A[12:0] provide the address, and the CARDREG* signal provides a chip select on the rising edge

for sampling the signals.

ENRMAP2:

Setting this bit will enable Address Re-Mapper 2.

TMPR3911 Datasheet(PDF) 144 Page - Toshiba Semiconductor

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