TMPR3911 datasheet(145/462 Pages) TOSHIBA

Part #	TMPR3911

Description	32-Bit TX System RISC TX39 Family

PDF	462 Pages

Scroll/Zoom	100%

Manufacturer	TOSHIBA [Toshiba Semiconductor]

Direct Link	http://www.semicon.toshiba.co.jp/eng

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145 / 462 page

Chapter 4 BIU Module

4-45

ENRMAP1:

Setting this bit will enable Address Re-Mapper 1.

ENWRINPAGE:

Setting this bit will cause the DRAMs and/or SDRAMs to remain in page mode when the

WrInPage signal is asserted by the CPU Interface. If this bit is cleared, the WrInPage signal is

ignored.

ENCS3USER:

Setting this bit will enable CS3 in the kuseg Space.

ENCS2USER:

Setting this bit will enable CS2 in the kuseg Space.

ENCS1USER:

Setting this bit will enable CS1 in the kuseg Space.

ENCS1DRAM:

Setting this bit will enable CS1 in Bank 1 and Bank 0 Space.

BANK1CONF[1:0]:

These bits provide the configuration for Bank 1 according to the following:

16-bit SDRAM

8-bit SDRAM

32-bit DRAM/HDRAM

16-bit DRAM/HDRAM

BANK0CONF[1:0]:

These bits provide the configuration for Bank 0 according to the following:

16-bit SDRAM

8-bit SDRAM

32-bit DRAM/HDRAM

16-bit DRAM/HDRAM

TMPR3911 Datasheet(PDF) 145 Page - Toshiba Semiconductor