TMPR3911 datasheet(149/462 Pages) TOSHIBA

149 / 462 page

Chapter 4 BIU Module

4-49

CS1ACCVAL1[3:0]:

These bits define the access time for CS1. If ENCS1PAGE is set, these bits will be used for the

first access and CS1ACCVAL2[3:0] will be used for the next three accesses for reads only. For

writes, only these bits are used. If ENCS1PAGE is not set, these bits and CS1ACCVAL2[3:0]

should be set with the same value. If ENCS1PAGE is set, these bits must be set to at least $1.

CS1ACCVAL2[3:0]:

These bits define the access time for the next three reads in a burst sequence if ENCS1PAGE is

set. If ENCS1PAGE is not set, these bits and CS1ACCVAL1[3:0] should be set with the same

value. If ENCS1PAGE is set, these bits must be set to at least $2.

CS0ACCVAL1[3:0]:

These bits define the access time for CS0. If ENCS0PAGE is set, these bits will be used for the

first access and CS0ACCVAL2[3:0] will be used for the next three accesses for reads only. For

writes, only these bits are used. If ENCS0PAGE is not set, these bits and CS0ACCVAL2[3:0]

should be set with the same value. If ENCS0PAGE is set, these bits must be set to at least $1.

CS0ACCVAL2[3:0]:

These bits define the access time for the next three reads in a burst sequence if ENCS0PAGE is

set. If ENCS0PAGE is not set, these bits and CS0ACCVAL1[3:0] should be set with the same

value. If ENCS0PAGE is set, these bits must be set to at least $2.

4.7.4

Memory Configuration 3 Register

OFFSET

= $00C

Bit

Label

RESET

Read/Write

31-28

CARD2ACCVAL[3:0]

R/W

27-24

CARD1ACCVAL[3:0]

R/W

23-20

CARD2IOACCVAL[3:0]

R/W

19-16

CARD1IOACCVAL[3:0]

R/W

ENMCS3PAGE

R/W

ENMCS2PAGE

R/W

ENMCS1PAGE

R/W

ENMCS0PAGE

R/W

ENCS3PAGE

R/W

ENCS2PAGE

R/W

ENCS1PAGE

R/W

ENCS0PAGE

R/W

CARD2WAITEN

R/W

CARD1WAITEN

R/W

5CARD2IOEN

R/W

4CARD1IOEN

R/W

3PORT8SEL

R/W

PORT2_8SEL

R/W

PORT1_8SEL

R/W

0DCLKDISABLE

R/W

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