TMPR3911 datasheet(152/462 Pages) TOSHIBA

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Chapter 4 BIU Module

4-52

ENBANK0HDRAM:

Setting this bit will enable the TMPR3911/12 to support HDRAM devices in Memory Bank 0.

The BANK0CONF bits in the Memory Configuration 0 Register will configure the TMPR3911/12

to support either a 16-bit HDRAM configuration or a 32-bit HDRAM configuration, in the same

manner that standard DRAM is setup.

ENARB:

Setting this bit will always cause the CPU Interface logic to externally arbitrate with the CPU

during DMA reads and writes when the DISSNOOP control bit is set.

DISSNOOP:

Setting this bit will prevent the CPU Interface logic from causing the SNOOP signal to assert to

the CPU Core during DMA writes.

CLRWRBUSERRINT:

WRBUSERRINT will occur whenever a write is timed out by the Watch Dog Timer.

This interrupt is connected directly to INT[0] on the CPU and is completely independent of the

rest of the TMPR3911/12 interrupt logic. When this interrupt is set, it will remain set until the

CLRWRBUSERRINT bit is asserted. The bit must be set and subsequently cleared to clear the

interrupt.

ENBANK1OPT:

Setting this bit will cause the BIU to insert an extra clock of delay between the assertion of

RAS1* and the assertion of the CAS* signals for DRAM accesses. This is needed for interfacing to

80 ns DRAMs when running with a clock greater than 70 MHz.

ENBANK0OPT:

Setting this bit will cause the BIU to insert an extra clock of delay between the assertion of

RAS0* and the assertion of the CAS* signals for DRAM accesses. This is needed for interfacing to

80 ns DRAMs when running with a clock greater than 70 MHz.

ENWATCH:

Setting this bit will enable the Watch Dog Timer.

WATCHTIMEVAL[3:0]:

These bits define the length of the Watch Dog Timer. The Watch Dog Timer rate is determined

by the following equation:

Watch Dog Timer Rate

(WATCHTIME

CLK

MEMPOWERDOWN:

Setting this bit will cause the memory interface to be put into Memory Power Down mode which

will cause the DRAMs and SDRAMs to be put into self-refresh and all memory signals will be

driven low. The memory interface will remain powered down until the processor attempts to access

a location in memory other than function registers.

TMPR3911 Datasheet(PDF) 152 Page - Toshiba Semiconductor