TMPR3911 datasheet(151/462 Pages) TOSHIBA

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Chapter 4 BIU Module

4-51

CARD1IOEN:

Setting this bit will cause accesses to Card 1 I/O space to assert the IORD* or IOWR* signals.

This is used for accessing I/O cards. If this bit is not set, RD* or WE* is asserted, which provides

Attribute space access.

PORT8SEL, PORT2_8SEL, PORT1_8SEL:

These bits define the PCMCIA port size.

PORT8SEL

PORT2_8SEL

PORT1_8SEL

Port1

Port2

8 bit port access

16 bit port access

8 bit port access

16 bit port access

DCLKDISABLE:

Setting this bit to 1 disables output of DCLKOUT. Clearing the bit to 0 enables output of

DCLKOUT except during memory power down (when MEMPORWERDOWN bit is set to 1).

4.7.5

Memory Configuration 4 Register

OFFSET

= $010

Bit

Label

RESET

Read/Write

ENBANK1HDRAM

R/W

ENBANK0HDRAM

R/W

ENARB

R/W

DISSNOOP

R/W

CLRWRBUSERRINT

R/W

ENBANK1OPT

R/W

ENBANK0OPT

R/W

ENWATCH

R/W

23-20

WATCHTIMEVAL[3:0]

R/W

19-17

Reserved

MEMPOWERDOWN

R/W

ENRFSH1

R/W

ENRFSH0

R/W

13-8

RFSHVAL1[5:0]

R/W

7-6

Reserved

5-0

RFSHVAL0[5:0]

R/W

ENBANK1HDRAM:

Setting this bit will enable the TMPR3911/12 to support HDRAM devices in Memory Bank 1.

The BANK1CONF bits in the Memory Configuration 0 Register will configure the TMPR3912 to

support either a 16-bit HDRAM configuration or a 32-bit HDRAM configuration, in the same

manner that standard DRAM is setup.

TMPR3911 Datasheet(PDF) 151 Page - Toshiba Semiconductor

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