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TMPR3911 Datasheet(PDF) 222 Page - Toshiba Semiconductor

Part # TMPR3911
Description  32-Bit TX System RISC TX39 Family
PDF  462 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3911 Datasheet(HTML) 222 Page - Toshiba Semiconductor

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Chapter 9 I/O Module
9-4
9.2.2
General Purpose I/O Ports
Each of the 7 general purpose I/O ports can be independently programmed as an input or output port.
Each port can generate a separate positive and negative edge interrupt. Figure 9.2.1 shows a block
diagram of a general purpose I/O port.
Each port consists of a bi-directional buffer connected to the appropriate TMPR3911/12 pin. For the
input direction, the output signal from the input buffer is routed directly to a debounce circuit. This
circuit performs a 16 ms to 24 ms debounce of the input signal. The debounce select control signal from
the I/O Debounce Select Register is used to select between the debouncer output and the direct signal
from the port input buffer, which bypasses the debouncer. This selected signal is then routed to the I/O
Data Input Register and to the Interrupt Flip-Flop. Reading a specific bit location within the I/O Data
Input Register returns the logic state of the respective general purpose I/O pin (either direct or
debounced), regardless of whether that pin is configured as an output or input. If the pin is configured as
an input, the value read is the logic state of the pin as driven by an external source. If the pin is
configured as an output, the value read is the logic state of the pin as driven by the TMPR3911/12.
For the output direction, the input signal to the output buffer is routed from the appropriate bit within
the I/O Data Output Register. The output enable control signal for the tri-state output buffer is routed
from the I/O Direction Register.
The I/O Power-Down Register provides independent control bits for controlling the power-down
state for each of the 7 general purpose I/O ports. If a particular I/O port is configured to power down,
then the output will be gated low and a Pull-Down resistor will be enabled whenever the device powers
down. Device power down occurs when either VCC3 or VCCON (internal signal) become de-asserted.
The Pull-Down will prevent the input from floating if the general purpose I/O port is configured as an
input.



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