TMPR3911 datasheet(218/462 Pages) TOSHIBA

Part #	TMPR3911

Description	32-Bit TX System RISC TX39 Family

PDF	462 Pages

Scroll/Zoom	100%

Manufacturer	TOSHIBA [Toshiba Semiconductor]

Direct Link	http://www.semicon.toshiba.co.jp/eng

Logo

218 / 462 page

Chapter 8 Interrupt Module

8-18

8.3.17

Enable Interrupt 6 Register

OFFSET

= $12C:

read/write

The Enable Interrupt 6 Register bit locations are mapped on a one to one basis with the Interrupt

Status 6 Register. A logic “1” written to a specific bit location will enable the corresponding

interrupt in the Status Register.

Bit

Label

RESET

Read/Write

31-19

Reserved

GLOBALEN

R/W

IRQPRITEST

R/W

IRQTEST

R/W

15-0

PRIORITYMASK[15:0]

R/W

GLOBALEN:

This is used as a global interrupt enable for all interrupts, and is cleared upon reset, therefore

disabling all interrupts.

IRQPRITEST:

This bit is used for IC testing and should not be set.

IRQTEST:

This bit is used for IC testing and should not be set.

PRIORITYMASK[15:0]:

These bits are an enable mask for the 16 possible high priority interrupts, where bit 15 is the

highest priority. A logic “1” written to a specific bit location will enable the corresponding high

priority interrupt.

TMPR3911 Datasheet(PDF) 218 Page - Toshiba Semiconductor