TMPR3911 datasheet(217/462 Pages) TOSHIBA

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Chapter 8 Interrupt Module

8-17

8.3.13

Enable Interrupt 2 Register

OFFSET

= $11C:

read/write

The Enable Interrupt 2 Register bit locations are mapped on a one to one basis with the Interrupt

Status 2 Register. A logic “1” written to a specific bit location will enable the corresponding

interrupt in the Status Register. This register is not cleared upon reset; however, the GLOBALEN

global interrupt enable bit is cleared upon reset, therefore disabling all interrupts.

8.3.14

Enable Interrupt 3 Register

OFFSET

= $120:

read/write

The Enable Interrupt 3 Register bit locations are mapped on a one to one basis with the Interrupt

Status 3 Register. A logic “1” written to a specific bit location will enable the corresponding

interrupt in the Status Register. This register is not cleared upon reset; however, the GLOBALEN

global interrupt enable bit is cleared upon reset, therefore disabling all interrupts.

8.3.15

Enable Interrupt 4 Register

OFFSET

= $124:

read/write

The Enable Interrupt 4 Register bit locations are mapped on a one to one basis with the Interrupt

Status 4 Register. A logic “1” written to a specific bit location will enable the corresponding

interrupt in the Status Register. This register is not cleared upon reset; however, the GLOBALEN

global interrupt enable bit is cleared upon reset, therefore disabling all interrupts.

8.3.16

Enable Interrupt 5 Register

OFFSET

= $128:

read/write

The Enable Interrupt 5 Register bit locations are mapped on a one to one basis with the Interrupt

Status 5 Register. A logic “1” written to a specific bit location will enable the corresponding

interrupt in the Status Register. This register is not cleared upon reset; however, the GLOBALEN

global interrupt enable bit is cleared upon reset, therefore disabling all interrupts.

TMPR3911 Datasheet(PDF) 217 Page - Toshiba Semiconductor