TMPR3911 datasheet(216/462 Pages) TOSHIBA

216 / 462 page

Chapter 8 Interrupt Module

8-16

8.3.7

Clear Interrupt 1 Register

OFFSET

= $100:

write-only

The Clear Interrupt 1 Register bit locations are mapped on a one to one basis with the Interrupt

Status 1 Register. A logic “1” written to a specific bit location will clear the corresponding bit in

the Status Register.

8.3.8

Clear Interrupt 2 Register

OFFSET

= $104:

write-only

The Clear Interrupt 2 Register bit locations are mapped on a one to one basis with the Interrupt

Status 2 Register. A logic “1” written to a specific bit location will clear the corresponding bit in

the Status Register.

8.3.9

Clear Interrupt 3 Register

OFFSET

= $108:

write-only

The Clear Interrupt 3 Register bit locations are mapped on a one to one basis with the Interrupt

Status 3 Register. A logic “1” written to a specific bit location will clear the corresponding bit in

the Status Register.

8.3.10

Clear Interrupt 4 Register

OFFSET

= $10C:

write-only

The Clear Interrupt 4 Register bit locations are mapped on a one to one basis with the Interrupt

Status 4 Register. A logic “1” written to a specific bit location will clear the corresponding bit in

the Status Register.

8.3.11

Clear Interrupt 5 Register

OFFSET

= $110:

write-only

The Clear Interrupt 5 Register bit locations are mapped on a one to one basis with the Interrupt

Status 5 Register. A logic “1” written to a specific bit location will clear the corresponding bit in

the Status Register.

8.3.12

Enable Interrupt 1 Register

OFFSET

= $118:

read/write

The Enable Interrupt 1 Register bit locations are mapped on a one to one basis with the Interrupt

Status 1 Register. A logic “1” written to a specific bit location will enable the corresponding

interrupt in the Status Register. This register is not cleared upon reset; however, the GLOBALEN

global interrupt enable bit is cleared upon reset, therefore disabling all interrupts.

TMPR3911 Datasheet(PDF) 216 Page - Toshiba Semiconductor

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