TMPR3911 datasheet(213/462 Pages) TOSHIBA

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Chapter 8 Interrupt Module

8-13

STPTIMERINT:

This interrupt is set whenever the Stop Timer Counter counts up to the value set by the

STPTIMERVAL[3:0] control bits.

POSPWRINT:

This interrupt is set whenever the PWRINT pin transitions from a logic “0” to a logic “1”.

NEGPWRINT:

This interrupt is set whenever the PWRINT pin transitions from a logic “1” to a logic “0”.

POSPWROKINT:

Issues an interrupt whenever the PWROK signal transitions from a logic “0” to a logic “1”.

NEGPWROKINT:

Issues an interrupt whenever the PWROK signal transitions from a logic “1” to a logic “0”.

POSONBUTNINT:

Issues an interrupt whenever the ONBUTN signal transitions from a logic “0” to a logic “1”. If

the DBNCONBUTN control bit is set, then the interrupt will not set until the signal is debounced

for 16-24 ms.

NEGONBUTNINT:

Issues an interrupt whenever the ONBUTN signal transitions from a logic “1” to a logic “0”. If

the DBNCONBUTN control bit is set, then the interrupt will not set until the signal is debounced

for 16-24 ms.

SPIBUFAVAILINT:

This interrupt is set whenever the ENSPI bit is first asserted and subsequently when the contents

of the SPI Transmitter Holding Register are transferred to the SPI Shift Register. This interrupt is

used to indicate that the SPI Transmitter Holding Register is available to be written by the

software.

SPIERRINT:

This interrupt is set whenever the SPI Transmitter Holding Register is written, but the

SPIBUFAVAILINT has not set to indicate that the register is available. This interrupt serves as an

overrun indication for the software.

TMPR3911 Datasheet(PDF) 213 Page - Toshiba Semiconductor