TMPR3911 datasheet(210/462 Pages) TOSHIBA

210 / 462 page

Chapter 8 Interrupt Module

8-10

UARTBEMPTYINT:

Issues an interrupt if the UARTB Transmit Holding Register and Transmit Shift Register are

both empty.

UARTBDMAFULLINT:

Issues an interrupt if the UARTB DMA counter reaches the end of the buffer.

UARTBDMAHALFINT:

Issues an interrupt if the UARTB DMA counter reaches the mid point of the buffer.

MBUSTXBUFAVAILINT:

This interrupt is set when the ENMBUS bit is first asserted and subsequently when the contents

of the MBUS Transmitter Holding Register are transferred to the MBUS Shift Register. This

interrupt is used to indicate that the MBUS Transmitter Holding Register is available to be written

by the software.

MBUSTXERRINT:

Issues an interrupt if the Magicbus Transmit Holding Register is written to when the Transmit

Holding Register is not available.

MBUSEMPTYINT:

Issues an interrupt if the Magicbus Transmit Holding Register and Transmit Shift Register are

both empty.

MBUSRXBUFAVAILINT:

Issues an interrupt if the Magicbus Receive Holding Register is loaded with data.

MBUSRXERRINT:

Issues an interrupt if the Magicbus Receive Holding Register is loaded twice before the interrupt

is serviced.

MBUSDETINT:

Issues an interrupt if the Magicbus Command Word detector triggers.

MBUSDMAFULLINT:

Issues an interrupt if the Magicbus DMA Counter reaches the end of the buffer.

MBUSDMAHALFINT:

Issues an interrupt if the Magicbus DMA Counter reaches the mid point of the buffer.

MBUSPOSINT:

Issues an interrupt if the MBUSINT signal goes from a logic “0” to a logic “1”.

MBUSNEGINT:

Issues an interrupt if the MBUSINT signal goes from a logic “1” to a logic “0”.

TMPR3911 Datasheet(PDF) 210 Page - Toshiba Semiconductor