TMPR3911 datasheet(207/462 Pages) TOSHIBA

207 / 462 page

Chapter 8 Interrupt Module

8-7

VALSNDPOSINT:

Issues an interrupt whenever the valid sound status flag transitions from a logic “0” to a logic

“1”. This valid flag is triggered from SIB subframe 0 (if SELSNDSF1

= “0”) or from SIB

subframe 1 (if SELSNDSF1

= “1”).

VALSNDNEGINT:

Issues an interrupt whenever the valid sound status flag transitions from a logic “1” to a logic

“0”. This valid flag is triggered from SIB subframe 0 (if SELSNDSF1

= “0”) or from SIB

subframe 1 (if SELSNDSF1

= “1”).

VALTELPOSINT:

Issues an interrupt whenever the valid telecom status flag transitions from a logic “0” to a logic

“1”. This valid flag is triggered from SIB subframe 0 (if SELTELSF1

= “0”) or from SIB subframe

1 (if SELTELSF1

= “1”).

VALTELNEGINT:

Issues an interrupt whenever the valid telecom status flag transitions from a logic “1” to a logic

“0”. This valid flag is triggered from SIB subframe 0 (if SELTELSF1

= “0”) or from SIB subframe

1 (if SELTELSF1

= “1”).

SNDININT:

Issues an interrupt whenever a valid sound input longword (32 bits) is available from the Sound

RX Holding Register; this also means a valid sound output longword can be written to the Sound

TX Holding Register.

TELININT:

Issues an interrupt whenever a valid telecom input longword (32 bits) is available from the

Telecom RX Holding Register; this also means a valid telecom output longword can be written to

the Telecom TX Holding Register.

SIBSF0INT:

Issues an interrupt at the start of every SIB subframe 0. This is used to initiate CPU reading of

the SIB Subframe 1 Status Register (SF1STAT Register) and/or CPU writing of the SIB Subframe

0 Control Register (SF0AUX Register).

SIBSF1INT:

Issues an interrupt at the start of every SIB subframe 1. This is used to initiate CPU reading of

the SIB Subframe 0 Status Register (SF0STAT Register) and/or CPU writing of the SIB Subframe

1 Control Register (SF1AUX Register).

SIBIRQPOSINT:

Issues an interrupt whenever the SIBIRQ pin transitions from a logic “0” to a logic “1”.

SIBIRQNEGINT:

Issues an interrupt whenever the SIBIRQ pin transitions from a logic “1” to a logic “0”.

TMPR3911 Datasheet(PDF) 207 Page - Toshiba Semiconductor

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