TMPR3911 datasheet(205/462 Pages) TOSHIBA

205 / 462 page

Chapter 8 Interrupt Module

8-5

8.3

Interrupt Registers

8.3.1

Interrupt Status 1 Register

OFFSET

= $100:

read-only

Bit

Label

RESET

Read/Write

LCDINT

–

DFINT

–

CHI0_5INT

–

CHI1_0INT

–

CHIDMACNTINT

–

CHININTA

–

CHININTB

–

CHIACTINT

–

CHIERRINT

–

SND0_5INT

–

SND1_0INT

–

TEL0_5INT

–

TEL1_0INT

–

SNDDMACNTINT

–

TELDMACNTINT

–

LSNDCLIPINT

–

RSNDCLIPINT

–

VALSNDPOSINT

–

VALSNDNEGINT

–

VALTELPOSINT

–

VALTELNEGINT

–

SNDININT

–

9TELININT

–

8SIBSF0INT

–

7SIBSF1INT

–

6SIBIRQNEGINT

–

5SIBIRQNEGINT

–

4-0

Reserved

–

LCDINT:

Issues an interrupt at the end of each video frame.

DFINT:

Issues an interrupt each time the video DF signal toggles.

CHI0_5INT:

Issues an interrupt whenever the CHI DMA buffer pointer has reached the halfway point.

CHI1_0INT:

Issues an interrupt whenever the CHI DMA buffer pointer has reached the end-of-buffer point.

CHIDMACNTINT:

Issues an interrupt each time the CHI DMA buffer pointer is incremented, which occurs

whenever a new CHI sample is read from and/or written to the CHI DMA buffer.

TMPR3911 Datasheet(PDF) 205 Page - Toshiba Semiconductor

TMPR3911 Datasheet(HTML) 205 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL