TMPR3911 datasheet(204/462 Pages) TOSHIBA

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Chapter 8 Interrupt Module

8-4

A given pending interrupt is cleared by writing a “1” to the corresponding bit position in the

corresponding Clear Interrupt Register. The output of this Clear Interrupt Register is used to reset the

corresponding Interrupt Status Register.

On power on reset, the Global Enable is cleared to prevent any interrupts from occurring until the

Enable Interrupt Registers are initialized. Also, all Clear Interrupts will be set for the duration of reset

(thus interrupts cleared).

The Interrupt Module also contains 15 High Priority Interrupt sources. A 16-bit Priority Mask

(located within the Enable Interrupt 6 Register) is used to enable any of these high priority interrupts, by

writing a “1” to the corresponding bit position in the Enable Interrupt 6 Register, where bit 15 is the

highest priority. Each bit of the 16-bit Priority Mask is gated with the corresponding 15 High Priority

Interrupt signals and these gated signals are then combined using a bitwise 16-input “OR” tree in order

to generate the IRQHIGH status signal. If IRQHIGH or IRQLOW is asserted, then the overall IRQ will

be asserted.

A Priority Encoder circuit also compares the 16-bit Priority Mask with the 15 High Priority Interrupt

signals and generates a 4-bit interrupt status vector which points to the highest priority pending interrupt

from the set of 16 possible events. Level 15 is the highest priority and Level 1 is the lowest priority,

with Level 0 corresponding to the standard interrupt handler.

The IRQHIGH signal is connected to interrupt bit 4 on the TX39/H Processor Core and the IRQLOW

signal is connected to interrupt bit 2. The IRQHIGH signal is also connected to CPU Co-Processor

Condition bit 3.

TMPR3911 Datasheet(PDF) 204 Page - Toshiba Semiconductor