TMPR3911 datasheet(200/462 Pages) TOSHIBA

200 / 462 page

Chapter 7 CHI Module

7-26

7.4.10

CHI TX Holding Register

OFFSET

= $1FC:

write-only

Bit

Label

RESET

Read/Write

31-0

CHITXHOLD[31:0]

CHITXHOLD[31:0]:

write-only

These bits represent the CHI data to be transmitted. CHI data can be either written directly to

this register by the CPU or transparently read from the CHI TX DMA buffer to this register. This

asserted. The write immediately after CHIININTA updates the internal TX holding register A and

the write immediately after CHIININTB updates the internal TX holding register B. Transmit data

for bytes 3, 2, 1, and 0 are loaded into the 32-bit CHITXHOLD at locations [31:24], [23:16],

[15:8], and [7:0], respectively. These data bytes correspond to the CHI timeslots as defined by the

values in the CHITXPTRA and CHITXPTRB TDM switch registers.

7.4.11

CHI RX Holding Register

OFFSET

= $1FC:

read-only

Bit

Label

RESET

Read/Write

31-0

CHIRXHOLD[31:0]

CHIRXHOLD[31:0]:

read-only

These bits represent the CHI data to be received. CHI data can be either read directly from this

The read immediately after CHIININTA sees the internal RX holding register A and the read

immediately after CHIININTB sees the internal RX holding register B. Receive data for bytes 3, 2,

1, and 0 are stored into the 32-bit CHIRXHOLD at locations [31:24], [23:16], [15:8], and [7:0],

respectively. These data bytes correspond to the CHI timeslots as defined by the values in the

CHIRXPTRA and CHIRXPTRB TDM switch registers.

TMPR3911 Datasheet(PDF) 200 Page - Toshiba Semiconductor