TMPR3911 datasheet(196/462 Pages) TOSHIBA

196 / 462 page

Chapter 7 CHI Module

7-22

7.4.5

CHI Transmit Pointer A Register

OFFSET

= $1E8:

write-only

Bit

Label

RESET

Read/Write

31-29

Reserved

28-24

CHITXPTRA3[4:0]

23-21

Reserved

20-16

CHITXPTRA2[4:0]

15-13

Reserved

12-8

CHITXPTRA1[4:0]

7-5

Reserved

4-0

CHITXPTRA0[4:0]

CHITXPTRA3[4:0]:

write-only

These bits represent the TDM switch pointer which defines the transmit channel timeslot for

byte 3 of the CHI transmit holding register A; register A handles all timeslots from channel 0 to

channel CHINCHAN.

CHITXPTRA2[4:0]:

write-only

These bits represent the TDM switch pointer which defines the transmit channel timeslot for

byte 2 of the CHI transmit holding register A; register A handles all timeslots from channel 0 to

channel CHINCHAN.

CHITXPTRA1[4:0]:

write-only

These bits represent the TDM switch pointer which defines the transmit channel timeslot for

byte 1 of the CHI transmit holding register A; register A handles all timeslots from channel 0 to

channel CHINCHAN.

CHITXPTRA0[4:0]:

write-only

These bits represent the TDM switch pointer which defines the transmit channel timeslot for

byte 0 of the CHI transmit holding register A; register A handles all timeslots from channel 0 to

channel CHINCHAN.

TMPR3911 Datasheet(PDF) 196 Page - Toshiba Semiconductor

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